minor JTAG init messaging tweaks

[fw/openocd] / src / target / cortex_m3.h

diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index ba61b1cba45ab08f1f44e4b86dd25a1ccf93df2e..4e8cd1116ccd992e480924b75489bc44a608f3c5 100644 (file)
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -80,7 +80,12 @@ extern char* cortex_m3_state_strings[];
 /* DCB_DEMCR bit and field definitions */
 #define        TRCENA                  (1 << 24)
 #define        VC_HARDERR              (1 << 10)
+#define        VC_INTERR               (1 << 9)
 #define        VC_BUSERR               (1 << 8)
+#define        VC_STATERR              (1 << 7)
+#define        VC_CHKERR               (1 << 6)
+#define        VC_NOCPERR              (1 << 5)
+#define        VC_MMERR                (1 << 4)
 #define        VC_CORERESET    (1 << 0)
 
 #define NVIC_ICTR              0xE000E004
@@ -117,21 +122,6 @@ extern char* cortex_m3_state_strings[];
 #define FPCR_REPLACE_BKPT_HIGH  (2 << 30)
 #define FPCR_REPLACE_BKPT_BOTH  (3 << 30)
 
-/* Use MRS/MSR to read/write any of these special registers.  Some of
- * them (xPSR, MSP, PSP) are always available using DCRxR.  Starting in
- * Cortex-M3 r2p0, some (CONTROL, BASEPRI, and *MASK) are also available
- * through DCRxR.
- * NOTE: this listing omits xPSR components and other mixtures.
- */
-#define SR_XPSR                3
-#define SR_MSP         8
-#define SR_PSP         9
-#define SR_PRIMASK     16
-#define SR_BASEPRI     17
-#define SR_BASEPRI_MAX 18
-#define SR_FAULTMASK   19
-#define SR_CONTROL     20
-
 typedef struct  cortex_m3_fp_comparator_s
 {
        int used;