/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
+ * *
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
/* NVIC_SHCSR bits */
#define SHCSR_BUSFAULTENA (1<<17)
/* NVIC_DFSR bits */
-#define DFSR_HALTED 1
-#define DFSR_BKPT 2
-#define DFSR_DWTTRAP 4
-#define DFSR_VCATCH 8
+#define DFSR_HALTED 1
+#define DFSR_BKPT 2
+#define DFSR_DWTTRAP 4
+#define DFSR_VCATCH 8
#define FPCR_CODE 0
#define FPCR_LITERAL 1
typedef struct cortex_m3_common_s
{
int common_magic;
-// int (*full_context)(struct target_s *target);
-
+
arm_jtag_t jtag_info;
/* Context information */
int intlinesnum;
u32 *intsetenable;
-/*
- u32 arm_bkpt;
- u16 thumb_bkpt;
- int sw_bkpts_use_wp;
- int wp_available;
- int wp0_used;
- int wp1_used;
-
- int force_hw_bkpts;
- int dbgreq_adjust_pc;
- int use_dbgrq;
- int has_etm;
-
- int reinit_embeddedice;
-
- struct working_area_s *dcc_working_area;
-
- int fast_memory_access;
- int dcc_downloads;
-*/
- /* breakpoint use map */
- int sw_bkpts_enabled;
-
armv7m_common_t armv7m;
swjdp_common_t swjdp_info;
-
void *arch_info;
} cortex_m3_common_t;
extern void cortex_m3_build_reg_cache(target_t *target);
-enum target_state cortex_m3_poll(target_t *target);
+int cortex_m3_poll(target_t *target);
int cortex_m3_halt(target_t *target);
int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
int cortex_m3_assert_reset(target_t *target);
int cortex_m3_deassert_reset(target_t *target);
int cortex_m3_soft_reset_halt(struct target_s *target);
-int cortex_m3_prepare_reset_halt(struct target_s *target);
int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);