PIC32: add flash algorithm support

[fw/openocd] / src / target / cortex_m3.c

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 7aec01513637bfe1653b9ae218d3a6577b48e764..d39d839c5371620bd2e6766f37a797650f7268d5 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -59,7 +59,7 @@ static void cortex_m3_enable_watchpoints(struct target *target);
 static int cortex_m3_store_core_reg_u32(struct target *target,
                enum armv7m_regtype type, uint32_t num, uint32_t value);
 
-static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
+static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
                uint32_t *value, int regnum)
 {
        int retval;
@@ -72,13 +72,19 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
 
        /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
-       dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
+       retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
-       dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
+       retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
+       if (retval != ERROR_OK)
+               return retval;
 
        retval = dap_run(swjdp);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* restore DCB_DCRDR - this needs to be in a seperate
         * transaction otherwise the emulated DCC channel breaks */
@@ -88,7 +94,7 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
        return retval;
 }
 
-static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
+static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
                uint32_t value, int regnum)
 {
        int retval;
@@ -101,11 +107,13 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
 
        /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
-       dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
+       retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
+       // XXX check retval
 
        /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
        dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
-       dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
+       retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
+       // XXX check retval
 
        retval = dap_run(swjdp);
 
@@ -121,7 +129,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target,
                uint32_t mask_on, uint32_t mask_off)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 
        /* mask off status bits */
        cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
@@ -134,7 +142,7 @@ static int cortex_m3_write_debug_halt_mask(struct target *target,
 static int cortex_m3_clear_halt(struct target *target)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 
        /* clear step if any */
        cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
@@ -152,7 +160,7 @@ static int cortex_m3_clear_halt(struct target *target)
 static int cortex_m3_single_step_core(struct target *target)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
        uint32_t dhcsr_save;
 
        /* backup dhcsr reg */
@@ -183,7 +191,7 @@ static int cortex_m3_endreset_event(struct target *target)
        uint32_t dcb_demcr;
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        struct armv7m_common *armv7m = &cortex_m3->armv7m;
-       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
        struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
        struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 
@@ -278,7 +286,7 @@ static int cortex_m3_examine_exception_reason(struct target *target)
 {
        uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
        struct armv7m_common *armv7m = target_to_armv7m(target);
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
        int retval;
 
        mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
@@ -352,7 +360,7 @@ static int cortex_m3_debug_entry(struct target *target)
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        struct armv7m_common *armv7m = &cortex_m3->armv7m;
        struct arm *arm = &armv7m->arm;
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
        struct reg *r;
 
        LOG_DEBUG(" ");
@@ -444,7 +452,7 @@ static int cortex_m3_poll(struct target *target)
        int retval;
        enum target_state prev_target_state = target->state;
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 
        /* Read from Debug Halting Control and Status Register */
        retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -579,7 +587,7 @@ static int cortex_m3_halt(struct target *target)
 static int cortex_m3_soft_reset_halt(struct target *target)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
        uint32_t dcb_dhcsr = 0;
        int retval, timeout = 0;
 
@@ -753,7 +761,7 @@ static int cortex_m3_step(struct target *target, int current,
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        struct armv7m_common *armv7m = &cortex_m3->armv7m;
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
        struct breakpoint *breakpoint = NULL;
        struct reg *pc = armv7m->arm.pc;
        bool bkpt_inst_found = false;
@@ -818,7 +826,7 @@ static int cortex_m3_step(struct target *target, int current,
 static int cortex_m3_assert_reset(struct target *target)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
        int assert_srst = 1;
 
        LOG_DEBUG("target->state: %s",
@@ -1368,7 +1376,7 @@ static int cortex_m3_load_core_reg_u32(struct target *target,
 {
        int retval;
        struct armv7m_common *armv7m = target_to_armv7m(target);
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
 
        /* NOTE:  we "know" here that the register identifiers used
         * in the v7m header match the Cortex-M3 Debug Core Register
@@ -1432,7 +1440,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
        int retval;
        uint32_t reg;
        struct armv7m_common *armv7m = target_to_armv7m(target);
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
 
 #ifdef ARMV7_GDB_HACKS
        /* If the LR register is being modified, make sure it will put us
@@ -1510,7 +1518,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
                uint32_t size, uint32_t count, uint8_t *buffer)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
        int retval = ERROR_INVALID_ARGUMENTS;
 
        /* cortex_m3 handles unaligned memory access */
@@ -1535,7 +1543,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
                uint32_t size, uint32_t count, uint8_t *buffer)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
        int retval = ERROR_INVALID_ARGUMENTS;
 
        if (count && buffer) {
@@ -1716,7 +1724,7 @@ static int cortex_m3_examine(struct target *target)
        uint32_t cpuid, fpcr;
        int i;
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
-       struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+       struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
 
        if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
                return retval;
@@ -1765,7 +1773,7 @@ static int cortex_m3_examine(struct target *target)
        return ERROR_OK;
 }
 
-static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
 {
        uint16_t dcrdr;
 
@@ -1790,7 +1798,7 @@ static int cortex_m3_target_request_data(struct target *target,
                uint32_t size, uint8_t *buffer)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
        uint8_t data;
        uint8_t ctrl;
        uint32_t i;
@@ -1810,7 +1818,7 @@ static int cortex_m3_handle_target_request(void *priv)
        if (!target_was_examined(target))
                return ERROR_OK;
        struct armv7m_common *armv7m = target_to_armv7m(target);
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
 
        if (!target->dbg_msg_enabled)
                return ERROR_OK;
@@ -1854,11 +1862,13 @@ static int cortex_m3_init_arch_info(struct target *target,
        cortex_m3->jtag_info.tap = tap;
        cortex_m3->jtag_info.scann_size = 4;
 
+       armv7m->arm.dap = &armv7m->dap;
+
        /* Leave (only) generic DAP stuff for debugport_init(); */
-       armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
-       armv7m->swjdp_info.memaccess_tck = 8;
+       armv7m->dap.jtag_info = &cortex_m3->jtag_info;
+       armv7m->dap.memaccess_tck = 8;
        /* Cortex-M3 has 4096 bytes autoincrement range */
-       armv7m->swjdp_info.tar_autoincr_block = (1 << 12);
+       armv7m->dap.tar_autoincr_block = (1 << 12);
 
        /* register arch-specific functions */
        armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
@@ -1928,7 +1938,7 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
        struct target *target = get_current_target(CMD_CTX);
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        struct armv7m_common *armv7m = &cortex_m3->armv7m;
-       struct swjdp_common *swjdp = &armv7m->swjdp_info;
+       struct adiv5_dap *swjdp = &armv7m->dap;
        uint32_t demcr = 0;
        int retval;