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arm_adi_v5: error propagation of mem_ap_read_atomic_u32 failure
[fw/openocd] / src / target / cortex_m3.c
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index d39d839c5371620bd2e6766f37a797650f7268d5..7bdf7d59a9a663e3c4caacd53002e148d7377bb8 100644 (file)
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -68,16 +68,22 @@ static int cortexm3_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
        /* because the DCB_DCRDR is used for the emulated dcc channel
         * we have to save/restore the DCB_DCRDR when used */
 
-       mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+       retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
-       dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+       retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+       if (retval != ERROR_OK)
+               return retval;
        retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
        if (retval != ERROR_OK)
                return retval;
 
        /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
-       dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+       retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+       if (retval != ERROR_OK)
+               return retval;
        retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
        if (retval != ERROR_OK)
                return retval;
@@ -103,15 +109,21 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
        /* because the DCB_DCRDR is used for the emulated dcc channel
         * we have to save/restore the DCB_DCRDR when used */
 
-       mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+       retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
-       dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+       retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+       if (retval != ERROR_OK)
+               return retval;
        retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
        // XXX check retval
 
        /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
-       dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+       retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+       if (retval != ERROR_OK)
+               return retval;
        retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
        // XXX check retval
 
@@ -143,12 +155,15 @@ static int cortex_m3_clear_halt(struct target *target)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
        struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+       int retval;
 
        /* clear step if any */
        cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
 
        /* Read Debug Fault Status Register */
-       mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+       retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* Clear Debug Fault Status */
        mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
@@ -196,14 +211,18 @@ static int cortex_m3_endreset_event(struct target *target)
        struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 
        /* REVISIT The four debug monitor bits are currently ignored... */
-       mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+       retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+       if (retval != ERROR_OK)
+               return retval;
        LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 
        /* this register is used for emulated dcc channel */
        mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
 
        /* Enable debug requests */
-       mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       if (retval != ERROR_OK)
+               return retval;
        if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
                mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 
@@ -250,7 +269,7 @@ static int cortex_m3_endreset_event(struct target *target)
        register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
        /* make sure we have latest dhcsr flags */
-       mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
 
        return retval;
 }
@@ -289,33 +308,51 @@ static int cortex_m3_examine_exception_reason(struct target *target)
        struct adiv5_dap *swjdp = &armv7m->dap;
        int retval;
 
-       mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+       retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+       if (retval != ERROR_OK)
+               return retval;
        switch (armv7m->exception_number)
        {
                case 2: /* NMI */
                        break;
                case 3: /* Hard Fault */
-                       mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+                       retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+                       if (retval != ERROR_OK)
+                               return retval;
                        if (except_sr & 0x40000000)
                        {
-                               mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+                               retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+                               if (retval != ERROR_OK)
+                                       return retval;
                        }
                        break;
                case 4: /* Memory Management */
-                       mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
-                       mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+                       retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+                       if (retval != ERROR_OK)
+                               return retval;
                        break;
                case 5: /* Bus Fault */
-                       mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
-                       mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+                       retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+                       if (retval != ERROR_OK)
+                               return retval;
                        break;
                case 6: /* Usage Fault */
-                       mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+                       retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+                       if (retval != ERROR_OK)
+                               return retval;
                        break;
                case 11:        /* SVCall */
                        break;
                case 12:        /* Debug Monitor */
-                       mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+                       retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+                       if (retval != ERROR_OK)
+                               return retval;
                        break;
                case 14:        /* PendSV */
                        break;
@@ -366,7 +403,9 @@ static int cortex_m3_debug_entry(struct target *target)
        LOG_DEBUG(" ");
 
        cortex_m3_clear_halt(target);
-       mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       if (retval != ERROR_OK)
+               return retval;
 
        if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
                return retval;
@@ -442,7 +481,11 @@ static int cortex_m3_debug_entry(struct target *target)
                target_state_name(target));
 
        if (armv7m->post_debug_entry)
-               armv7m->post_debug_entry(target);
+       {
+               retval = armv7m->post_debug_entry(target);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
 
        return ERROR_OK;
 }
@@ -474,13 +517,17 @@ static int cortex_m3_poll(struct target *target)
                target->debug_reason = DBG_REASON_DBGRQ;
 
                /* refresh status bits */
-               mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+               retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+               if (retval != ERROR_OK)
+                       return retval;
        }
 
        if (cortex_m3->dcb_dhcsr & S_RESET_ST)
        {
                /* check if still in reset */
-               mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+               retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+               if (retval != ERROR_OK)
+                       return retval;
 
                if (cortex_m3->dcb_dhcsr & S_RESET_ST)
                {
@@ -608,8 +655,10 @@ static int cortex_m3_soft_reset_halt(struct target *target)
                retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
                if (retval == ERROR_OK)
                {
-                       mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
+                       retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
                                        &cortex_m3->nvic_dfsr);
+                       if (retval != ERROR_OK)
+                               return retval;
                        if ((dcb_dhcsr & S_HALT)
                                        && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
                        {
@@ -801,7 +850,10 @@ static int cortex_m3_step(struct target *target, int current,
                cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
        }
 
-       mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       int retval;
+       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* registers are now invalid */
        register_cache_invalidate(cortex_m3->armv7m.core_cache);
@@ -813,7 +865,9 @@ static int cortex_m3_step(struct target *target, int current,
                        " nvic_icsr = 0x%" PRIx32,
                        cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 
-       cortex_m3_debug_entry(target);
+       retval = cortex_m3_debug_entry(target);
+       if (retval != ERROR_OK)
+               return retval;
        target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 
        LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
@@ -843,7 +897,10 @@ static int cortex_m3_assert_reset(struct target *target)
                assert_srst = 0;
 
        /* Enable debug requests */
-       mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       int retval;
+       retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+       if (retval != ERROR_OK)
+               return retval;
        if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
                mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
 
@@ -945,7 +1002,9 @@ static int cortex_m3_assert_reset(struct target *target)
                         * after reset) on LM3S6918 -- Michael Schwingen
                         */
                        uint32_t tmp;
-                       mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+                       retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+                       if (retval != ERROR_OK)
+                               return retval;
                }
        }
 
@@ -956,7 +1015,6 @@ static int cortex_m3_assert_reset(struct target *target)
 
        if (target->reset_halt)
        {
-               int retval;
                if ((retval = target_halt(target)) != ERROR_OK)
                        return retval;
        }
@@ -1876,7 +1934,6 @@ static int cortex_m3_init_arch_info(struct target *target,
        armv7m->post_debug_entry = NULL;
 
        armv7m->pre_restore_context = NULL;
-       armv7m->post_restore_context = NULL;
 
        armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
        armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
@@ -1946,7 +2003,9 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
        if (retval != ERROR_OK)
                return retval;
 
-       mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+       retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+       if (retval != ERROR_OK)
+               return retval;
 
        if (CMD_ARGC > 0) {
                unsigned catch = 0;
@@ -1983,7 +2042,9 @@ write:
 
                /* write, but don't assume it stuck (why not??) */
                mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
-               mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+               retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+               if (retval != ERROR_OK)
+                       return retval;
 
                /* FIXME be sure to clear DEMCR on clean server shutdown.
                 * Otherwise the vector catch hardware could fire when there's
openocd with support for Altus Metrum targets