#include "arm_disassembler.h"
+/* NOTE: most of this should work fine for the Cortex-M1 and
+ * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
+ */
+
#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
/* forward declarations */
-static int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-static int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
+static int cortex_m3_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
+static int cortex_m3_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint);
static void cortex_m3_enable_watchpoints(struct target_s *target);
static int cortex_m3_store_core_reg_u32(target_t *target,
enum armv7m_regtype type, uint32_t num, uint32_t value);
#ifdef ARMV7_GDB_HACKS
extern uint8_t armv7m_gdb_dummy_cpsr_value[];
-extern reg_t armv7m_gdb_dummy_cpsr_reg;
+extern struct reg armv7m_gdb_dummy_cpsr_reg;
#endif
-static int cortex_m3_has_mmu(struct target_s *target, bool *has_mmu)
-{
- *has_mmu = false;
- return ERROR_OK;
-}
-
-static int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp,
+static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
uint32_t *value, int regnum)
{
int retval;
return retval;
}
-static int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp,
+static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
uint32_t value, int regnum)
{
int retval;
static int cortex_m3_write_debug_halt_mask(target_t *target,
uint32_t mask_on, uint32_t mask_off)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
static int cortex_m3_clear_halt(target_t *target)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
static int cortex_m3_single_step_core(target_t *target)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
uint32_t dhcsr_save;
/* backup dhcsr reg */
{
int i;
uint32_t dcb_demcr;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
- cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
- cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
+ struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
static int cortex_m3_examine_debug_reason(target_t *target)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason */
/* only check the debug reason if we don't know it already */
static int cortex_m3_examine_exception_reason(target_t *target)
{
uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
switch (armv7m->exception_number)
int i;
uint32_t xPSR;
int retval;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct armv7m_common *armv7m = &cortex_m3->armv7m;
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
LOG_DEBUG(" ");
{
int retval;
enum target_state prev_target_state = target->state;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
/* Read from Debug Halting Control and Status Register */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
static int cortex_m3_soft_reset_halt(struct target_s *target)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
static void cortex_m3_enable_breakpoints(struct target_s *target)
{
- breakpoint_t *breakpoint = target->breakpoints;
+ struct breakpoint *breakpoint = target->breakpoints;
/* set any pending breakpoints */
while (breakpoint)
static int cortex_m3_resume(struct target_s *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- breakpoint_t *breakpoint = NULL;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct breakpoint *breakpoint = NULL;
uint32_t resume_pc;
if (target->state != TARGET_HALTED)
static int cortex_m3_step(struct target_s *target, int current,
uint32_t address, int handle_breakpoints)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
- breakpoint_t *breakpoint = NULL;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct armv7m_common *armv7m = &cortex_m3->armv7m;
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct breakpoint *breakpoint = NULL;
if (target->state != TARGET_HALTED)
{
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
- buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
+ buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value,
+ 0, 32, address);
/* the front-end may request us not to handle breakpoints */
- if (handle_breakpoints)
- if ((breakpoint = breakpoint_find(target, buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32))))
+ if (handle_breakpoints) {
+ breakpoint = breakpoint_find(target, buf_get_u32(armv7m
+ ->core_cache->reg_list[15].value, 0, 32));
+ if (breakpoint)
cortex_m3_unset_breakpoint(target, breakpoint);
+ }
target->debug_reason = DBG_REASON_SINGLESTEP;
static int cortex_m3_assert_reset(target_t *target)
{
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
}
static int
-cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+cortex_m3_set_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
{
int retval;
int fp_num = 0;
uint32_t hilo;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
-
- cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_fp_comparator *comparator_list = cortex_m3->fp_comparator_list;
if (breakpoint->set)
{
}
static int
-cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+cortex_m3_unset_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
{
int retval;
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- cortex_m3_fp_comparator_t * comparator_list = cortex_m3->fp_comparator_list;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_fp_comparator * comparator_list = cortex_m3->fp_comparator_list;
if (!breakpoint->set)
{
}
static int
-cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+cortex_m3_add_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
if (cortex_m3->auto_bp_type)
{
}
static int
-cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+cortex_m3_remove_breakpoint(struct target_s *target, struct breakpoint *breakpoint)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* REVISIT why check? FBP can be updated with core running ... */
if (target->state != TARGET_HALTED)
}
static int
-cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_set_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
int dwt_num = 0;
uint32_t mask, temp;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* watchpoint params were validated earlier */
mask = 0;
* watchpoint using comparator #1; comparator #0 matching cycle
* count; send data trace info through ITM and TPIU; etc
*/
- cortex_m3_dwt_comparator_t *comparator;
+ struct cortex_m3_dwt_comparator *comparator;
for (comparator = cortex_m3->dwt_comparator_list;
comparator->used && dwt_num < cortex_m3->dwt_num_comp;
}
static int
-cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_unset_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- cortex_m3_dwt_comparator_t *comparator;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct cortex_m3_dwt_comparator *comparator;
int dwt_num;
if (!watchpoint->set)
}
static int
-cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_add_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* REVISIT why check? DWT can be updated with core running ... */
if (target->state != TARGET_HALTED)
}
static int
-cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+cortex_m3_remove_watchpoint(struct target_s *target, struct watchpoint *watchpoint)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
/* REVISIT why check? DWT can be updated with core running ... */
if (target->state != TARGET_HALTED)
static void cortex_m3_enable_watchpoints(struct target_s *target)
{
- watchpoint_t *watchpoint = target->watchpoints;
+ struct watchpoint *watchpoint = target->watchpoints;
/* set any pending watchpoints */
while (watchpoint)
enum armv7m_regtype type, uint32_t num, uint32_t * value)
{
int retval;
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
{
int retval;
uint32_t reg;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
static int cortex_m3_read_memory(struct target_s *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
int retval;
/* sanitize arguments */
static int cortex_m3_write_memory(struct target_s *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
int retval;
/* sanitize arguments */
uint32_t value; /* scratch/cache */
};
-static int cortex_m3_dwt_get_reg(struct reg_s *reg)
+static int cortex_m3_dwt_get_reg(struct reg *reg)
{
struct dwt_reg_state *state = reg->arch_info;
return target_read_u32(state->target, state->addr, &state->value);
}
-static int cortex_m3_dwt_set_reg(struct reg_s *reg, uint8_t *buf)
+static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
{
struct dwt_reg_state *state = reg->arch_info;
static int dwt_reg_type = -1;
static void
-cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d)
+cortex_m3_dwt_addreg(struct target_s *t, struct reg *r, struct dwt_reg *d)
{
struct dwt_reg_state *state;
}
static void
-cortex_m3_dwt_setup(cortex_m3_common_t *cm3, struct target_s *target)
+cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target_s *target)
{
uint32_t dwtcr;
- struct reg_cache_s *cache;
- cortex_m3_dwt_comparator_t *comparator;
+ struct reg_cache *cache;
+ struct cortex_m3_dwt_comparator *comparator;
int reg, i;
target_read_u32(target, DWT_CTRL, &dwtcr);
cm3->dwt_num_comp = (dwtcr >> 28) & 0xF;
cm3->dwt_comp_available = cm3->dwt_num_comp;
cm3->dwt_comparator_list = calloc(cm3->dwt_num_comp,
- sizeof(cortex_m3_dwt_comparator_t));
+ sizeof(struct cortex_m3_dwt_comparator));
if (!cm3->dwt_comparator_list) {
fail0:
cm3->dwt_num_comp = 0;
*register_get_last_cache_p(&target->reg_cache) = cache;
cm3->dwt_cache = cache;
- LOG_INFO("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
+ LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
dwtcr, cm3->dwt_num_comp,
(dwtcr & (0xf << 24)) ? " only" : "/trigger");
int retval;
uint32_t cpuid, fpcr;
int i;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
return retval;
cortex_m3->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF); /* bits [14:12] and [7:4] */
cortex_m3->fp_num_lit = (fpcr >> 8) & 0xF;
cortex_m3->fp_code_available = cortex_m3->fp_num_code;
- cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(cortex_m3_fp_comparator_t));
+ cortex_m3->fp_comparator_list = calloc(cortex_m3->fp_num_code + cortex_m3->fp_num_lit, sizeof(struct cortex_m3_fp_comparator));
cortex_m3->fpb_enabled = fpcr & 1;
for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
{
return ERROR_OK;
}
-static int cortex_m3_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_m3_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
{
uint16_t dcrdr;
static int cortex_m3_target_request_data(target_t *target,
uint32_t size, uint8_t *buffer)
{
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
uint8_t data;
uint8_t ctrl;
uint32_t i;
target_t *target = priv;
if (!target_was_examined(target))
return ERROR_OK;
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
if (!target->dbg_msg_enabled)
return ERROR_OK;
}
static int cortex_m3_init_arch_info(target_t *target,
- cortex_m3_common_t *cortex_m3, jtag_tap_t *tap)
+ struct cortex_m3_common *cortex_m3, struct jtag_tap *tap)
{
int retval;
- armv7m_common_t *armv7m;
- armv7m = &cortex_m3->armv7m;
+ struct armv7m_common *armv7m = &cortex_m3->armv7m;
armv7m_init_arch_info(target, armv7m);
armv7m->swjdp_info.memaccess_tck = 8;
armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
- /* initialize arch-specific breakpoint handling */
-
- cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
- cortex_m3->arch_info = NULL;
-
/* register arch-specific functions */
armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
armv7m->pre_restore_context = NULL;
armv7m->post_restore_context = NULL;
- armv7m->arch_info = cortex_m3;
armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
static int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
{
- cortex_m3_common_t *cortex_m3 = calloc(1,sizeof(cortex_m3_common_t));
+ struct cortex_m3_common *cortex_m3 = calloc(1,sizeof(struct cortex_m3_common));
+ cortex_m3->common_magic = CORTEX_M3_COMMON_MAGIC;
cortex_m3_init_arch_info(target, cortex_m3, target->tap);
return ERROR_OK;
}
+/*--------------------------------------------------------------------------*/
+
+static int cortex_m3_verify_pointer(struct command_context_s *cmd_ctx,
+ struct cortex_m3_common *cm3)
+{
+ if (cm3->common_magic != CORTEX_M3_COMMON_MAGIC) {
+ command_print(cmd_ctx, "target is not a Cortex-M3");
+ return ERROR_TARGET_INVALID;
+ }
+ return ERROR_OK;
+}
+
+/*
+ * Only stuff below this line should need to verify that its target
+ * is a Cortex-M3. Everything else should have indirected through the
+ * cortexm3_target structure, which is only used with CM3 targets.
+ */
+
/*
* REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
* as at least ARM-1156T2. The interesting thing about Cortex-M is
* that *only* Thumb2 disassembly matters. There are also some small
* additions to Thumb2 that are specific to ARMv7-M.
*/
-static int
-handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx,
- char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_cortex_m3_disassemble_command)
{
- int retval = ERROR_OK;
+ int retval;
target_t *target = get_current_target(cmd_ctx);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
uint32_t address;
unsigned long count = 1;
- arm_instruction_t cur_instruction;
+ struct arm_instruction cur_instruction;
+
+ retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
+ if (retval != ERROR_OK)
+ return retval;
errno = 0;
switch (argc) {
case 2:
- count = strtoul(args[1], NULL, 0);
- if (errno)
- return ERROR_FAIL;
+ COMMAND_PARSE_NUMBER(ulong, args[1], count);
/* FALL THROUGH */
case 1:
- address = strtoul(args[0], NULL, 0);
- if (errno)
- return ERROR_FAIL;
+ COMMAND_PARSE_NUMBER(u32, args[0], address);
break;
default:
command_print(cmd_ctx,
{ "reset", VC_CORERESET, },
};
-static int
-handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx,
- char *cmd, char **argv, int argc)
+COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
{
target_t *target = get_current_target(cmd_ctx);
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ struct armv7m_common *armv7m = &cortex_m3->armv7m;
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
uint32_t demcr = 0;
+ int retval;
int i;
+ retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
+ if (retval != ERROR_OK)
+ return retval;
+
mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
if (argc > 0) {
unsigned catch = 0;
if (argc == 1) {
- if (strcmp(argv[0], "all") == 0) {
+ if (strcmp(args[0], "all") == 0) {
catch = VC_HARDERR | VC_INTERR | VC_BUSERR
| VC_STATERR | VC_CHKERR | VC_NOCPERR
| VC_MMERR | VC_CORERESET;
goto write;
- } else if (strcmp(argv[0], "none") == 0) {
+ } else if (strcmp(args[0], "none") == 0) {
goto write;
}
}
while (argc-- > 0) {
for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
- if (strcmp(argv[argc], vec_ids[i].name) != 0)
+ if (strcmp(args[argc], vec_ids[i].name) != 0)
continue;
catch |= vec_ids[i].mask;
break;
}
if (i == ARRAY_SIZE(vec_ids)) {
- LOG_ERROR("No CM3 vector '%s'", argv[argc]);
+ LOG_ERROR("No CM3 vector '%s'", args[argc]);
return ERROR_INVALID_ARGUMENTS;
}
}
return ERROR_OK;
}
-static int
-handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx,
- char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_cortex_m3_mask_interrupts_command)
{
target_t *target = get_current_target(cmd_ctx);
- armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ int retval;
+
+ retval = cortex_m3_verify_pointer(cmd_ctx, cortex_m3);
+ if (retval != ERROR_OK)
+ return retval;
if (target->state != TARGET_HALTED)
{
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
+ command_print(cmd_ctx, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
return retval;
}
-target_type_t cortexm3_target =
+struct target_type cortexm3_target =
{
.name = "cortex_m3",
.register_commands = cortex_m3_register_commands,
.target_create = cortex_m3_target_create,
.init_target = cortex_m3_init_target,
- .has_mmu = cortex_m3_has_mmu,
.examine = cortex_m3_examine,
};
-
projects / fw / openocd / blobdiff