/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
- mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
if (retval != ERROR_OK)
return retval;
/* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
if (retval != ERROR_OK)
return retval;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
- mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
// XXX check retval
/* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
- dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
// XXX check retval
uint32_t mask_on, uint32_t mask_off)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
static int cortex_m3_clear_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ int retval;
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
/* Read Debug Fault Status Register */
- mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ if (retval != ERROR_OK)
+ return retval;
/* Clear Debug Fault Status */
- mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
+ retval = mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
return ERROR_OK;
static int cortex_m3_single_step_core(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
uint32_t dhcsr_save;
+ int retval;
/* backup dhcsr reg */
dhcsr_save = cortex_m3->dcb_dhcsr;
* HALT can put the core into an unknown state.
*/
if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
- mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+ {
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
- mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+ if (retval != ERROR_OK)
+ return retval;
+ }
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG(" ");
/* restore dhcsr reg */
uint32_t dcb_demcr;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
/* REVISIT The four debug monitor bits are currently ignored... */
- mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
/* this register is used for emulated dcc channel */
- mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+ retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+ if (retval != ERROR_OK)
+ return retval;
/* Enable debug requests */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ {
+ retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ if (retval != ERROR_OK)
+ return retval;
+ }
/* clear any interrupt masking */
cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
* choices *EXCEPT* explicitly scripted overrides like "vector_catch"
* or manual updates to the NVIC SHCSR and CCR registers.
*/
- mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
+ retval = mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
+ if (retval != ERROR_OK)
+ return retval;
/* Paranoia: evidently some (early?) chips don't preserve all the
* debug state (including FBP, DWT, etc) across reset...
*/
/* Enable FPB */
- target_write_u32(target, FP_CTRL, 3);
+ retval = target_write_u32(target, FP_CTRL, 3);
+ if (retval != ERROR_OK)
+ return retval;
+
cortex_m3->fpb_enabled = 1;
/* Restore FPB registers */
for (i = 0; i < cortex_m3->fp_num_code + cortex_m3->fp_num_lit; i++)
{
- target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
+ retval = target_write_u32(target, fp_list[i].fpcr_address, fp_list[i].fpcr_value);
+ if (retval != ERROR_OK)
+ return retval;
}
/* Restore DWT registers */
for (i = 0; i < cortex_m3->dwt_num_comp; i++)
{
- target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
+ retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 0,
dwt_list[i].comp);
- target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 4,
dwt_list[i].mask);
- target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
dwt_list[i].function);
+ if (retval != ERROR_OK)
+ return retval;
}
retval = dap_run(swjdp);
if (retval != ERROR_OK)
register_cache_invalidate(cortex_m3->armv7m.core_cache);
/* make sure we have latest dhcsr flags */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
return retval;
}
{
uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
int retval;
- mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+ retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
+ if (retval != ERROR_OK)
+ return retval;
switch (armv7m->exception_number)
{
case 2: /* NMI */
break;
case 3: /* Hard Fault */
- mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+ retval = mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
if (except_sr & 0x40000000)
{
- mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
+ if (retval != ERROR_OK)
+ return retval;
}
break;
case 4: /* Memory Management */
- mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 5: /* Bus Fault */
- mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
- mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 6: /* Usage Fault */
- mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ retval = mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
- mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+ retval = mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
+ if (retval != ERROR_OK)
+ return retval;
break;
case 14: /* PendSV */
break;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
struct arm *arm = &armv7m->arm;
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
struct reg *r;
LOG_DEBUG(" ");
cortex_m3_clear_halt(target);
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
return retval;
target_state_name(target));
if (armv7m->post_debug_entry)
- armv7m->post_debug_entry(target);
+ {
+ retval = armv7m->post_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
return ERROR_OK;
}
int retval;
enum target_state prev_target_state = target->state;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
/* Read from Debug Halting Control and Status Register */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
target->debug_reason = DBG_REASON_DBGRQ;
/* refresh status bits */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
}
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
/* check if still in reset */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
static int cortex_m3_soft_reset_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
/* Enter debug state on reset; restore DEMCR in endreset_event() */
- mem_ap_write_u32(swjdp, DCB_DEMCR,
+ retval = mem_ap_write_u32(swjdp, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ if (retval != ERROR_OK)
+ return retval;
/* Request a core-only reset */
- mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+ retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
AIRCR_VECTKEY | AIRCR_VECTRESET);
+ if (retval != ERROR_OK)
+ return retval;
target->state = TARGET_RESET;
/* registers are now invalid */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
if (retval == ERROR_OK)
{
- mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
+ retval = mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
&cortex_m3->nvic_dfsr);
+ if (retval != ERROR_OK)
+ return retval;
if ((dcb_dhcsr & S_HALT)
&& (cortex_m3->nvic_dfsr & DFSR_VCATCH))
{
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
struct breakpoint *breakpoint = NULL;
struct reg *pc = armv7m->arm.pc;
bool bkpt_inst_found = false;
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
}
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ int retval;
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
/* registers are now invalid */
register_cache_invalidate(cortex_m3->armv7m.core_cache);
" nvic_icsr = 0x%" PRIx32,
cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
- cortex_m3_debug_entry(target);
+ retval = cortex_m3_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
static int cortex_m3_assert_reset(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
- int assert_srst = 1;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
LOG_DEBUG("target->state: %s",
target_state_name(target));
* requiring SRST, getting a SoC reset (or a core-only reset)
* instead of a system reset.
*/
- if (!(jtag_reset_config & RESET_HAS_SRST))
- assert_srst = 0;
+ if (!(jtag_reset_config & RESET_HAS_SRST) &&
+ (cortex_m3->soft_reset_config == CORTEX_M3_RESET_SRST)) {
+ reset_config = CORTEX_M3_RESET_VECTRESET;
+ }
/* Enable debug requests */
- mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ int retval;
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK)
+ return retval;
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ {
+ retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ if (retval != ERROR_OK)
+ return retval;
+ }
- mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+ retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
+ if (retval != ERROR_OK)
+ return retval;
if (!target->reset_halt)
{
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m3->dcb_dhcsr & C_MASKINTS)
- mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+ {
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
DBGKEY | C_DEBUGEN | C_HALT);
+ if (retval != ERROR_OK)
+ return retval;
+ }
/* clear any debug flags before resuming */
cortex_m3_clear_halt(target);
* bad vector table entries. Should this include MMERR or
* other flags too?
*/
- mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ if (retval != ERROR_OK)
+ return retval;
}
- /*
- * When nRST is asserted on most Stellaris devices, it clears some of
- * the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
- * and OpenOCD depends on those TRMs. So we won't use SRST on those
- * chips. (Only power-on reset should affect debug state, beyond a
- * few specified bits; not the chip's nRST input, wired to SRST.)
- *
- * REVISIT current errata specs don't seem to cover this issue.
- * Do we have more details than this email?
- * https://lists.berlios.de/pipermail
- * /openocd-development/2008-August/003065.html
- */
- if (strcmp(target->variant, "lm3s") == 0)
- {
- /* Check for silicon revisions with the issue. */
- uint32_t did0;
-
- if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
- {
- switch ((did0 >> 16) & 0xff)
- {
- case 0:
- /* all Sandstorm suffer issue */
- assert_srst = 0;
- break;
-
- case 1:
- case 3:
- /* Fury and DustDevil rev A have
- * this nRST problem. It should
- * be fixed in rev B silicon.
- */
- if (((did0 >> 8) & 0xff) == 0)
- assert_srst = 0;
- break;
- case 4:
- /* Tempest should be fine. */
- break;
- }
- }
- }
-
- if (assert_srst)
+ if (reset_config == CORTEX_M3_RESET_SRST)
{
/* default to asserting srst */
if (jtag_reset_config & RESET_SRST_PULLS_TRST)
else
{
/* Use a standard Cortex-M3 software reset mechanism.
- * SYSRESETREQ will reset SoC peripherals outside the
- * core, like watchdog timers, if the SoC wires it up
- * correctly. Else VECRESET can reset just the core.
+ * We default to using VECRESET as it is supported on all current cores.
+ * This has the disadvantage of not resetting the peripherals, so a
+ * reset-init event handler is needed to perform any peripheral resets.
*/
- mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
- AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
- LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
+ retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+ AIRCR_VECTKEY | ((reset_config == CORTEX_M3_RESET_SYSRESETREQ)
+ ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
+ if (retval != ERROR_OK)
+ return retval;
+
+ LOG_DEBUG("Using Cortex-M3 %s", (reset_config == CORTEX_M3_RESET_SYSRESETREQ)
+ ? "SYSRESETREQ" : "VECTRESET");
+
+ if (reset_config == CORTEX_M3_RESET_VECTRESET) {
+ LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
+ "handler to reset any peripherals");
+ }
{
/* I do not know why this is necessary, but it
* after reset) on LM3S6918 -- Michael Schwingen
*/
uint32_t tmp;
- mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+ retval = mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+ if (retval != ERROR_OK)
+ return retval;
}
}
if (target->reset_halt)
{
- int retval;
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
if (breakpoint->type == BKPT_HARD)
cortex_m3->fp_code_available--;
- cortex_m3_set_breakpoint(target, breakpoint);
- return ERROR_OK;
+ return cortex_m3_set_breakpoint(target, breakpoint);
}
static int
{
int retval;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
int retval;
uint32_t reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
int retval = ERROR_INVALID_ARGUMENTS;
/* cortex_m3 handles unaligned memory access */
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
int retval = ERROR_INVALID_ARGUMENTS;
if (count && buffer) {
uint32_t cpuid, fpcr;
int i;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.swjdp_info;
+ struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
return retval;
static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
{
uint16_t dcrdr;
+ int retval;
mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
*ctrl = (uint8_t)dcrdr;
if (dcrdr & (1 << 0))
{
dcrdr = 0;
- mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+ retval = mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+ if (retval != ERROR_OK)
+ return retval;
}
return ERROR_OK;
uint32_t size, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
uint8_t data;
uint8_t ctrl;
uint32_t i;
if (!target_was_examined(target))
return ERROR_OK;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
if (!target->dbg_msg_enabled)
return ERROR_OK;
cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
+ /* default reset mode is to use srst if fitted
+ * if not it will use CORTEX_M3_RESET_VECTRESET */
+ cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
+
+ armv7m->arm.dap = &armv7m->dap;
+
/* Leave (only) generic DAP stuff for debugport_init(); */
- armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
- armv7m->swjdp_info.memaccess_tck = 8;
+ armv7m->dap.jtag_info = &cortex_m3->jtag_info;
+ armv7m->dap.memaccess_tck = 8;
/* Cortex-M3 has 4096 bytes autoincrement range */
- armv7m->swjdp_info.tar_autoincr_block = (1 << 12);
+ armv7m->dap.tar_autoincr_block = (1 << 12);
/* register arch-specific functions */
armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
armv7m->post_debug_entry = NULL;
armv7m->pre_restore_context = NULL;
- armv7m->post_restore_context = NULL;
armv7m->load_core_reg_u32 = cortex_m3_load_core_reg_u32;
armv7m->store_core_reg_u32 = cortex_m3_store_core_reg_u32;
struct target *target = get_current_target(CMD_CTX);
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct adiv5_dap *swjdp = &armv7m->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7m->dap;
uint32_t demcr = 0;
int retval;
if (retval != ERROR_OK)
return retval;
- mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ if (retval != ERROR_OK)
+ return retval;
if (CMD_ARGC > 0) {
unsigned catch = 0;
demcr |= catch;
/* write, but don't assume it stuck (why not??) */
- mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
- mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ retval = mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ if (retval != ERROR_OK)
+ return retval;
/* FIXME be sure to clear DEMCR on clean server shutdown.
* Otherwise the vector catch hardware could fire when there's
return ERROR_OK;
}
+COMMAND_HANDLER(handle_cortex_m3_reset_config_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+ int retval;
+ char *reset_config;
+
+ retval = cortex_m3_verify_pointer(CMD_CTX, cortex_m3);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (CMD_ARGC > 0)
+ {
+ if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
+ cortex_m3->soft_reset_config = CORTEX_M3_RESET_SYSRESETREQ;
+ else if (strcmp(*CMD_ARGV, "vectreset") == 0)
+ cortex_m3->soft_reset_config = CORTEX_M3_RESET_VECTRESET;
+ else
+ cortex_m3->soft_reset_config = CORTEX_M3_RESET_SRST;
+ }
+
+ switch (cortex_m3->soft_reset_config)
+ {
+ case CORTEX_M3_RESET_SRST:
+ reset_config = "srst";
+ break;
+
+ case CORTEX_M3_RESET_SYSRESETREQ:
+ reset_config = "sysresetreq";
+ break;
+
+ case CORTEX_M3_RESET_VECTRESET:
+ reset_config = "vectreset";
+ break;
+
+ default:
+ reset_config = "unknown";
+ break;
+ }
+
+ command_print(CMD_CTX, "cortex_m3 reset_config %s", reset_config);
+
+ return ERROR_OK;
+}
+
static const struct command_registration cortex_m3_exec_command_handlers[] = {
{
.name = "maskisr",
.help = "configure hardware vectors to trigger debug entry",
.usage = "['all'|'none'|('bus_err'|'chk_err'|...)*]",
},
+ {
+ .name = "reset_config",
+ .handler = handle_cortex_m3_reset_config_command,
+ .mode = COMMAND_ANY,
+ .help = "configure software reset handling",
+ .usage = "['srst'|'sysresetreq'|'vectreset']",
+ },
COMMAND_REGISTRATION_DONE
};
static const struct command_registration cortex_m3_command_handlers[] = {
projects / fw / openocd / blobdiff