target/cortex_m: cumulate DHCSR sticky bits

[fw/openocd] / src / target / cortex_m.h

diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index a767f93c513ba42dde4ca48df462a560e75c36ac..a5dfbf856aef0aea68f5922373622d3881b13a56 100644 (file)
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -35,23 +35,49 @@
 #define ITM_TER0       0xE0000E00
 #define ITM_TPR                0xE0000E40
 #define ITM_TCR                0xE0000E80
+#define ITM_TCR_ITMENA_BIT     BIT(0)
+#define ITM_TCR_BUSY_BIT       BIT(23)
 #define ITM_LAR                0xE0000FB0
 #define ITM_LAR_KEY    0xC5ACCE55
 
 #define CPUID          0xE000ED00
 
-#define ARM_CPUID_PARTNO_MASK  0xFFF0
+#define ARM_CPUID_PARTNO_POS    4
+#define ARM_CPUID_PARTNO_MASK  (0xFFF << ARM_CPUID_PARTNO_POS)
+
+enum cortex_m_partno {
+       CORTEX_M0_PARTNO   = 0xC20,
+       CORTEX_M1_PARTNO   = 0xC21,
+       CORTEX_M3_PARTNO   = 0xC23,
+       CORTEX_M4_PARTNO   = 0xC24,
+       CORTEX_M7_PARTNO   = 0xC27,
+       CORTEX_M0P_PARTNO  = 0xC60,
+       CORTEX_M23_PARTNO  = 0xD20,
+       CORTEX_M33_PARTNO  = 0xD21,
+       CORTEX_M35P_PARTNO = 0xD31,
+       CORTEX_M55_PARTNO  = 0xD22,
+};
+
+/* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
+#define CORTEX_M_F_HAS_FPV4               BIT(0)
+#define CORTEX_M_F_HAS_FPV5               BIT(1)
+#define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K  BIT(2)
 
-#define CORTEX_M23_PARTNO      0xD200
-#define CORTEX_M33_PARTNO      0xD210
+struct cortex_m_part_info {
+       enum cortex_m_partno partno;
+       const char *name;
+       enum arm_arch arch;
+       uint32_t flags;
+};
 
 /* Debug Control Block */
 #define DCB_DHCSR      0xE000EDF0
 #define DCB_DCRSR      0xE000EDF4
 #define DCB_DCRDR      0xE000EDF8
 #define DCB_DEMCR      0xE000EDFC
+#define DCB_DSCSR      0xE000EE08
 
-#define DCRSR_WnR      BIT(16)
+#define DCRSR_WNR      BIT(16)
 
 #define DWT_CTRL       0xE0001000
 #define DWT_CYCCNT     0xE0001004
@@ -114,19 +140,25 @@
 #define VC_MMERR               BIT(4)
 #define VC_CORERESET   BIT(0)
 
+/* DCB_DSCSR bit and field definitions */
+#define DSCSR_CDS              BIT(16)
+
+/* NVIC registers */
 #define NVIC_ICTR              0xE000E004
 #define NVIC_ISE0              0xE000E100
 #define NVIC_ICSR              0xE000ED04
 #define NVIC_AIRCR             0xE000ED0C
 #define NVIC_SHCSR             0xE000ED24
 #define NVIC_CFSR              0xE000ED28
-#define NVIC_MMFSRb            0xE000ED28
-#define NVIC_BFSRb             0xE000ED29
-#define NVIC_USFSRh            0xE000ED2A
+#define NVIC_MMFSRB            0xE000ED28
+#define NVIC_BFSRB             0xE000ED29
+#define NVIC_USFSRH            0xE000ED2A
 #define NVIC_HFSR              0xE000ED2C
 #define NVIC_DFSR              0xE000ED30
 #define NVIC_MMFAR             0xE000ED34
 #define NVIC_BFAR              0xE000ED38
+#define NVIC_SFSR              0xE000EDE4
+#define NVIC_SFAR              0xE000EDE8
 
 /* NVIC_AIRCR bits */
 #define AIRCR_VECTKEY          (0x5FAul << 16)
@@ -181,28 +213,29 @@ struct cortex_m_common {
 
        /* Context information */
        uint32_t dcb_dhcsr;
+       uint32_t dcb_dhcsr_cumulated_sticky;
        uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
        uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 
        /* Flash Patch and Breakpoint (FPB) */
-       int fp_num_lit;
-       int fp_num_code;
+       unsigned int fp_num_lit;
+       unsigned int fp_num_code;
        int fp_rev;
        bool fpb_enabled;
        struct cortex_m_fp_comparator *fp_comparator_list;
 
        /* Data Watchpoint and Trace (DWT) */
-       int dwt_num_comp;
-       int dwt_comp_available;
+       unsigned int dwt_num_comp;
+       unsigned int dwt_comp_available;
        uint32_t dwt_devarch;
        struct cortex_m_dwt_comparator *dwt_comparator_list;
        struct reg_cache *dwt_cache;
 
        enum cortex_m_soft_reset_config soft_reset_config;
        bool vectreset_supported;
-
        enum cortex_m_isrmasking_mode isrmasking_mode;
 
+       const struct cortex_m_part_info *core_info;
        struct armv7m_common armv7m;
 
        int apsel;
@@ -224,13 +257,10 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
 int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
 int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint);
 int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpoint);
-int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint);
-int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *watchpoint);
 int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint);
 int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpoint);
 void cortex_m_enable_breakpoints(struct target *target);
 void cortex_m_enable_watchpoints(struct target *target);
-void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target);
 void cortex_m_deinit_target(struct target *target);
 int cortex_m_profiling(struct target *target, uint32_t *samples,
        uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);