cmd: add missing usage vars

[fw/openocd] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 8000b9a81a169fb29a8121b780c9393527dba9e1..f181060ab08a0ed42f165872fcaab92925171710 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -59,9 +59,6 @@
 
 
 /* forward declarations */
-static int cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
-static int cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
-static void cortex_m3_enable_watchpoints(struct target *target);
 static int cortex_m3_store_core_reg_u32(struct target *target,
                enum armv7m_regtype type, uint32_t num, uint32_t value);
 
@@ -124,16 +121,20 @@ static int cortexm3_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
        if (retval != ERROR_OK)
                return retval;
        retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
-       // XXX check retval
+       if (retval != ERROR_OK)
+               return retval;
 
        /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
        retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
        if (retval != ERROR_OK)
                return retval;
        retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
-       // XXX check retval
+       if (retval != ERROR_OK)
+               return retval;
 
        retval = dap_run(swjdp);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* restore DCB_DCRDR - this needs to be in a seperate
         * transaction otherwise the emulated DCC channel breaks */
@@ -337,7 +338,7 @@ static int cortex_m3_examine_debug_reason(struct target *target)
 
 static int cortex_m3_examine_exception_reason(struct target *target)
 {
-       uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
+       uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct adiv5_dap *swjdp = &armv7m->dap;
        int retval;
@@ -1138,7 +1139,7 @@ static int cortex_m3_deassert_reset(struct target *target)
        return ERROR_OK;
 }
 
-static int
+int
 cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        int retval;
@@ -1213,7 +1214,7 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
        return ERROR_OK;
 }
 
-static int
+int
 cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        int retval;
@@ -1268,7 +1269,7 @@ cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
        return ERROR_OK;
 }
 
-static int
+int
 cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
@@ -1318,7 +1319,7 @@ cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
        return cortex_m3_set_breakpoint(target, breakpoint);
 }
 
-static int
+int
 cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
@@ -1346,7 +1347,7 @@ cortex_m3_remove_breakpoint(struct target *target, struct breakpoint *breakpoint
        return ERROR_OK;
 }
 
-static int
+int
 cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
        int dwt_num = 0;
@@ -1411,7 +1412,7 @@ cortex_m3_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
        return ERROR_OK;
 }
 
-static int
+int
 cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
@@ -1448,7 +1449,7 @@ cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
        return ERROR_OK;
 }
 
-static int
+int
 cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
@@ -1499,7 +1500,7 @@ cortex_m3_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
        return ERROR_OK;
 }
 
-static int
+int
 cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
@@ -1522,7 +1523,7 @@ cortex_m3_remove_watchpoint(struct target *target, struct watchpoint *watchpoint
        return ERROR_OK;
 }
 
-static void cortex_m3_enable_watchpoints(struct target *target)
+void cortex_m3_enable_watchpoints(struct target *target)
 {
        struct watchpoint *watchpoint = target->watchpoints;
 
@@ -1592,7 +1593,7 @@ static int cortex_m3_load_core_reg_u32(struct target *target,
                break;
 
        default:
-               return ERROR_INVALID_ARGUMENTS;
+               return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        return ERROR_OK;
@@ -1672,7 +1673,7 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
                break;
 
        default:
-               return ERROR_INVALID_ARGUMENTS;
+               return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        return ERROR_OK;
@@ -1683,7 +1684,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct adiv5_dap *swjdp = &armv7m->dap;
-       int retval = ERROR_INVALID_ARGUMENTS;
+       int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
        /* cortex_m3 handles unaligned memory access */
        if (count && buffer) {
@@ -1708,7 +1709,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct adiv5_dap *swjdp = &armv7m->dap;
-       int retval = ERROR_INVALID_ARGUMENTS;
+       int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
        if (count && buffer) {
                switch (size) {
@@ -1816,7 +1817,7 @@ cortex_m3_dwt_addreg(struct target *t, struct reg *r, struct dwt_reg *d)
        r->type = &dwt_reg_type;
 }
 
-static void
+void
 cortex_m3_dwt_setup(struct cortex_m3_common *cm3, struct target *target)
 {
        uint32_t dwtcr;
@@ -2143,7 +2144,7 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
                        }
                        if (i == ARRAY_SIZE(vec_ids)) {
                                LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
-                               return ERROR_INVALID_ARGUMENTS;
+                               return ERROR_COMMAND_SYNTAX_ERROR;
                        }
                }
 write:
@@ -2298,6 +2299,7 @@ static const struct command_registration cortex_m3_command_handlers[] = {
                .name = "cortex_m3",
                .mode = COMMAND_EXEC,
                .help = "Cortex-M3 command group",
+               .usage = "",
                .chain = cortex_m3_exec_command_handlers,
        },
        COMMAND_REGISTRATION_DONE