target/cortex_m: use cortex_m->dcb_dhcsr in cortex_m_soft_reset_halt()

[fw/openocd] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index f3c8527cf3c81f7640e2d6533e26ea28cb6b1f3b..d4affa6831fdcd202031d99d9817b72dae0df03c 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -34,6 +34,7 @@
 #include "cortex_m.h"
 #include "target_request.h"
 #include "target_type.h"
+#include "arm_adi_v5.h"
 #include "arm_disassembler.h"
 #include "register.h"
 #include "arm_opcodes.h"
@@ -300,7 +301,6 @@ static int cortex_m_clear_halt(struct target *target)
 static int cortex_m_single_step_core(struct target *target)
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
-       struct armv7m_common *armv7m = &cortex_m->armv7m;
        int retval;
 
        /* Mask interrupts before clearing halt, if not done already.  This avoids
@@ -308,13 +308,11 @@ static int cortex_m_single_step_core(struct target *target)
         * HALT can put the core into an unknown state.
         */
        if (!(cortex_m->dcb_dhcsr & C_MASKINTS)) {
-               retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
-                               DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
+               retval = cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
                if (retval != ERROR_OK)
                        return retval;
        }
-       retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
-                       DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
+       retval = cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
        if (retval != ERROR_OK)
                return retval;
        LOG_DEBUG(" ");
@@ -778,7 +776,6 @@ static int cortex_m_soft_reset_halt(struct target *target)
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
        struct armv7m_common *armv7m = &cortex_m->armv7m;
-       uint32_t dcb_dhcsr = 0;
        int retval, timeout = 0;
 
        /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
@@ -814,25 +811,23 @@ static int cortex_m_soft_reset_halt(struct target *target)
        register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 
        while (timeout < 100) {
-               retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &dcb_dhcsr);
+               retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DHCSR, &cortex_m->dcb_dhcsr);
                if (retval == ERROR_OK) {
                        retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_DFSR,
                                        &cortex_m->nvic_dfsr);
                        if (retval != ERROR_OK)
                                return retval;
-                       if ((dcb_dhcsr & S_HALT)
+                       if ((cortex_m->dcb_dhcsr & S_HALT)
                                && (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
-                               LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
-                                       "DFSR 0x%08x",
-                                       (unsigned) dcb_dhcsr,
-                                       (unsigned) cortex_m->nvic_dfsr);
+                               LOG_DEBUG("system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
+                                       cortex_m->dcb_dhcsr, cortex_m->nvic_dfsr);
                                cortex_m_poll(target);
                                /* FIXME restore user's vector catch config */
                                return ERROR_OK;
                        } else
                                LOG_DEBUG("waiting for system reset-halt, "
-                                       "DHCSR 0x%08x, %d ms",
-                                       (unsigned) dcb_dhcsr, timeout);
+                                       "DHCSR 0x%08" PRIx32 ", %d ms",
+                                       cortex_m->dcb_dhcsr, timeout);
                }
                timeout++;
                alive_sleep(1);
@@ -1243,7 +1238,7 @@ static int cortex_m_assert_reset(struct target *target)
                retval = ERROR_OK;
        } else {
                /* Use a standard Cortex-M3 software reset mechanism.
-                * We default to using VECRESET as it is supported on all current cores
+                * We default to using VECTRESET as it is supported on all current cores
                 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
                 * This has the disadvantage of not resetting the peripherals, so a
                 * reset-init event handler is needed to perform any peripheral resets.
@@ -2081,8 +2076,12 @@ int cortex_m_examine(struct target *target)
 
                armv7m->arm.arch = cortex_m->core_info->arch;
 
-               LOG_DEBUG("%s r%" PRId8 "p%" PRId8 " processor detected",
-                               cortex_m->core_info->name, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
+               LOG_INFO("%s: %s r%" PRId8 "p%" PRId8 " processor detected",
+                               target_name(target),
+                               cortex_m->core_info->name,
+                               (uint8_t)((cpuid >> 20) & 0xf),
+                               (uint8_t)((cpuid >> 0) & 0xf));
+
                cortex_m->maskints_erratum = false;
                if (core_partno == CORTEX_M7_PARTNO) {
                        uint8_t rev, patch;
@@ -2191,7 +2190,7 @@ int cortex_m_examine(struct target *target)
                cortex_m_dwt_setup(cortex_m, target);
 
                /* These hardware breakpoints only work for code in flash! */
-               LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
+               LOG_INFO("%s: target has %d breakpoints, %d watchpoints",
                        target_name(target),
                        cortex_m->fp_num_code,
                        cortex_m->dwt_num_comp);