cortex_m, hla_target: do not try asserting SRST if it's not present

[fw/openocd] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 9e4dcb644ae86071189dbe150feb86ece4e08cbd..9521085b1cc8724ae51e7abf5c59791fc03080f3 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -425,8 +425,9 @@ static int cortex_m3_debug_entry(struct target *target)
        int num_regs = arm->core_cache->num_regs;
 
        for (i = 0; i < num_regs; i++) {
-               if (!armv7m->arm.core_cache->reg_list[i].valid)
-                       armv7m->read_core_reg(target, i);
+               r = &armv7m->arm.core_cache->reg_list[i];
+               if (!r->valid)
+                       arm->read_core_reg(target, r, i, ARM_MODE_ANY);
        }
 
        r = arm->core_cache->reg_list + ARMV7M_xPSR;
@@ -988,7 +989,8 @@ static int cortex_m3_assert_reset(struct target *target)
 
        bool srst_asserted = false;
 
-       if (jtag_reset_config & RESET_SRST_NO_GATING) {
+       if ((jtag_reset_config & RESET_HAS_SRST) &&
+           (jtag_reset_config & RESET_SRST_NO_GATING)) {
                adapter_assert_reset();
                srst_asserted = true;
        }
@@ -1619,7 +1621,7 @@ static int cortex_m3_read_memory(struct target *target, uint32_t address,
        if (count && buffer) {
                switch (size) {
                        case 4:
-                               retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
+                               retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address, true);
                                break;
                        case 2:
                                retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
@@ -1649,7 +1651,7 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
        if (count && buffer) {
                switch (size) {
                        case 4:
-                               retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
+                               retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address, true);
                                break;
                        case 2:
                                retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
@@ -1663,12 +1665,6 @@ static int cortex_m3_write_memory(struct target *target, uint32_t address,
        return retval;
 }
 
-static int cortex_m3_bulk_write_memory(struct target *target, uint32_t address,
-       uint32_t count, const uint8_t *buffer)
-{
-       return cortex_m3_write_memory(target, address, 4, count, buffer);
-}
-
 static int cortex_m3_init_target(struct command_context *cmd_ctx,
        struct target *target)
 {
@@ -1801,6 +1797,9 @@ fail1:
                for (j = 0; j < 3; j++, reg++)
                        cortex_m3_dwt_addreg(target, cache->reg_list + reg,
                                dwt_comp + 3 * i + j);
+
+               /* make sure we clear any watchpoints enabled on the target */
+               target_write_u32(target, comparator->dwt_comparator_address + 8, 0);
        }
 
        *register_get_last_cache_p(&target->reg_cache) = cache;
@@ -1892,6 +1891,9 @@ int cortex_m3_examine(struct target *target)
                        cortex_m3->fp_comparator_list[i].type =
                                (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
                        cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
+
+                       /* make sure we clear any breakpoints enabled on the target */
+                       target_write_u32(target, cortex_m3->fp_comparator_list[i].fpcr_address, 0);
                }
                LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
                        fpcr,
@@ -2255,9 +2257,9 @@ static const struct command_registration cortex_m3_command_handlers[] = {
                .chain = armv7m_command_handlers,
        },
        {
-               .name = "cortex_m3",
+               .name = "cortex_m",
                .mode = COMMAND_EXEC,
-               .help = "Cortex-M3 command group",
+               .help = "Cortex-M command group",
                .usage = "",
                .chain = cortex_m3_exec_command_handlers,
        },
@@ -2265,7 +2267,8 @@ static const struct command_registration cortex_m3_command_handlers[] = {
 };
 
 struct target_type cortexm3_target = {
-       .name = "cortex_m3",
+       .name = "cortex_m",
+       .deprecated_name = "cortex_m3",
 
        .poll = cortex_m3_poll,
        .arch_state = armv7m_arch_state,
@@ -2284,7 +2287,6 @@ struct target_type cortexm3_target = {
 
        .read_memory = cortex_m3_read_memory,
        .write_memory = cortex_m3_write_memory,
-       .bulk_write_memory = cortex_m3_bulk_write_memory,
        .checksum_memory = armv7m_checksum_memory,
        .blank_check_memory = armv7m_blank_check_memory,