target/cortex_m,hla_target: rework Cortex-M register handling part 4

[fw/openocd] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 4df903e661e210c29df09b9db3f8a96c33cbc772..72a2bd322e5f8ed89d942729c40d1cd1a7b01462 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -56,8 +56,8 @@ static int cortex_m_store_core_reg_u32(struct target *target,
                uint32_t num, uint32_t value);
 static void cortex_m_dwt_free(struct target *target);
 
-static int cortexm_dap_read_coreregister_u32(struct target *target,
-       uint32_t *value, int regnum)
+static int cortex_m_load_core_reg_u32(struct target *target,
+               uint32_t regsel, uint32_t *value)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        int retval;
@@ -71,7 +71,7 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
                        return retval;
        }
 
-       retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regnum);
+       retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRSR, regsel);
        if (retval != ERROR_OK)
                return retval;
 
@@ -89,8 +89,8 @@ static int cortexm_dap_read_coreregister_u32(struct target *target,
        return retval;
 }
 
-static int cortexm_dap_write_coreregister_u32(struct target *target,
-       uint32_t value, int regnum)
+static int cortex_m_store_core_reg_u32(struct target *target,
+               uint32_t regsel, uint32_t value)
 {
        struct armv7m_common *armv7m = target_to_armv7m(target);
        int retval;
@@ -108,7 +108,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regnum | DCRSR_WnR);
+       retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRSR, regsel | DCRSR_WnR);
        if (retval != ERROR_OK)
                return retval;
 
@@ -1606,168 +1606,6 @@ void cortex_m_enable_watchpoints(struct target *target)
        }
 }
 
-static int cortex_m_load_core_reg_u32(struct target *target,
-               uint32_t regsel, uint32_t *value)
-{
-       int retval;
-
-       switch (regsel) {
-               case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
-                       /* read a normal core register */
-                       retval = cortexm_dap_read_coreregister_u32(target, value, regsel);
-
-                       if (retval != ERROR_OK) {
-                               LOG_ERROR("JTAG failure %i", retval);
-                               return ERROR_JTAG_DEVICE_ERROR;
-                       }
-                       LOG_DEBUG("load from core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
-                       break;
-
-               case ARMV7M_REGSEL_FPSCR:
-                       /* Floating-point Status and Registers */
-                       retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       retval = target_read_u32(target, DCB_DCRDR, value);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       LOG_DEBUG("load from FPSCR  value 0x%" PRIx32, *value);
-                       break;
-
-               case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
-                       /* Floating-point Status and Registers */
-                       retval = target_write_u32(target, DCB_DCRSR, regsel);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       retval = target_read_u32(target, DCB_DCRDR, value);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       LOG_DEBUG("load from FPU reg S%d  value 0x%" PRIx32,
-                                 (int)(regsel - ARMV7M_REGSEL_S0), *value);
-                       break;
-
-               case ARMV7M_PRIMASK:
-               case ARMV7M_BASEPRI:
-               case ARMV7M_FAULTMASK:
-               case ARMV7M_CONTROL:
-                       /* Cortex-M3 packages these four registers as bitfields
-                        * in one Debug Core register.  So say r0 and r2 docs;
-                        * it was removed from r1 docs, but still works.
-                        */
-                       cortexm_dap_read_coreregister_u32(target, value, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
-
-                       switch (regsel) {
-                               case ARMV7M_PRIMASK:
-                                       *value = buf_get_u32((uint8_t *)value, 0, 1);
-                                       break;
-
-                               case ARMV7M_BASEPRI:
-                                       *value = buf_get_u32((uint8_t *)value, 8, 8);
-                                       break;
-
-                               case ARMV7M_FAULTMASK:
-                                       *value = buf_get_u32((uint8_t *)value, 16, 1);
-                                       break;
-
-                               case ARMV7M_CONTROL:
-                                       *value = buf_get_u32((uint8_t *)value, 24, 3);
-                                       break;
-                       }
-
-                       LOG_DEBUG("load from special reg %" PRIu32 " value 0x%" PRIx32 "", regsel, *value);
-                       break;
-
-               default:
-                       return ERROR_COMMAND_SYNTAX_ERROR;
-       }
-
-       return ERROR_OK;
-}
-
-static int cortex_m_store_core_reg_u32(struct target *target,
-               uint32_t regsel, uint32_t value)
-{
-       int retval;
-       uint32_t reg;
-       struct armv7m_common *armv7m = target_to_armv7m(target);
-
-       switch (regsel) {
-               case ARMV7M_REGSEL_R0 ... ARMV7M_REGSEL_PSP:
-                       retval = cortexm_dap_write_coreregister_u32(target, value, regsel);
-                       if (retval != ERROR_OK) {
-                               struct reg *r;
-
-                               LOG_ERROR("JTAG failure");
-                               r = armv7m->arm.core_cache->reg_list + regsel; /* TODO: don't use regsel as register index */
-                               r->dirty = r->valid;
-                               return ERROR_JTAG_DEVICE_ERROR;
-                       }
-                       LOG_DEBUG("write core reg %" PRIu32 " value 0x%" PRIx32 "", regsel, value);
-                       break;
-
-               case ARMV7M_REGSEL_FPSCR:
-                       /* Floating-point Status and Registers */
-                       retval = target_write_u32(target, DCB_DCRDR, value);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       retval = target_write_u32(target, DCB_DCRSR, ARMV7M_REGSEL_FPSCR | DCRSR_WnR);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
-                       break;
-
-               case ARMV7M_REGSEL_S0 ... ARMV7M_REGSEL_S31:
-                       /* Floating-point Status and Registers */
-                       retval = target_write_u32(target, DCB_DCRDR, value);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       retval = target_write_u32(target, DCB_DCRSR, regsel | DCRSR_WnR);
-                       if (retval != ERROR_OK)
-                               return retval;
-                       LOG_DEBUG("write FPU reg S%d  value 0x%" PRIx32,
-                                 (int)(regsel - ARMV7M_REGSEL_S0), value);
-                       break;
-
-               case ARMV7M_PRIMASK:
-               case ARMV7M_BASEPRI:
-               case ARMV7M_FAULTMASK:
-               case ARMV7M_CONTROL:
-                       /* Cortex-M3 packages these four registers as bitfields
-                        * in one Debug Core register.  So say r0 and r2 docs;
-                        * it was removed from r1 docs, but still works.
-                        */
-                       cortexm_dap_read_coreregister_u32(target, &reg, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
-
-                       switch (regsel) {
-                               case ARMV7M_PRIMASK:
-                                       buf_set_u32((uint8_t *)&reg, 0, 1, value);
-                                       break;
-
-                               case ARMV7M_BASEPRI:
-                                       buf_set_u32((uint8_t *)&reg, 8, 8, value);
-                                       break;
-
-                               case ARMV7M_FAULTMASK:
-                                       buf_set_u32((uint8_t *)&reg, 16, 1, value);
-                                       break;
-
-                               case ARMV7M_CONTROL:
-                                       buf_set_u32((uint8_t *)&reg, 24, 3, value);
-                                       break;
-                       }
-
-                       cortexm_dap_write_coreregister_u32(target, reg, ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL);
-
-                       LOG_DEBUG("write special reg %" PRIu32 " value 0x%" PRIx32 " ", regsel, value);
-                       break;
-
-               default:
-                       return ERROR_COMMAND_SYNTAX_ERROR;
-       }
-
-       return ERROR_OK;
-}
-
 static int cortex_m_read_memory(struct target *target, target_addr_t address,
        uint32_t size, uint32_t count, uint8_t *buffer)
 {