uint32_t mask_on, uint32_t mask_off)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
static int cortex_m3_clear_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
int retval;
/* clear step if any */
static int cortex_m3_single_step_core(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
uint32_t dhcsr_save;
int retval;
uint32_t dcb_demcr;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
{
uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
retval = mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
struct arm *arm = &armv7m->arm;
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
struct reg *r;
LOG_DEBUG(" ");
int retval = ERROR_OK;
enum target_state prev_target_state = target->state;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
/* Read from Debug Halting Control and Status Register */
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
static int cortex_m3_soft_reset_halt(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
struct breakpoint *breakpoint = NULL;
struct reg *pc = armv7m->arm.pc;
bool bkpt_inst_found = false;
*
*/
- /* Set a temporary break point */
- retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
- bool tmp_bp_set = (retval == ERROR_OK);
-
- /* No more breakpoints left, just do a step */
- if (!tmp_bp_set)
+ /* 2012-09-29 ph
+ *
+ * If a break point is already set on the lower half word then a break point on
+ * the upper half word will not break again when the core is restarted. So we
+ * just step over the instruction with interrupts disabled.
+ *
+ * The documentation has no information about this, it was found by observation
+ * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
+ * suffer from this problem.
+ *
+ * To add some confusion: pc_value has bit 0 always set, while the breakpoint
+ * address has it always cleared. The former is done to indicate thumb mode
+ * to gdb.
+ *
+ */
+ if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
+ LOG_DEBUG("Stepping over next instruction with interrupts disabled");
+ cortex_m3_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+ /* Re-enable interrupts */
+ cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+ }
else {
- /* Start the core */
- LOG_DEBUG("Starting core to serve pending interrupts");
- int64_t t_start = timeval_ms();
- cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
-
- /* Wait for pending handlers to complete or timeout */
- do {
- retval = mem_ap_read_atomic_u32(swjdp,
- DCB_DHCSR,
- &cortex_m3->dcb_dhcsr);
- if (retval != ERROR_OK) {
- target->state = TARGET_UNKNOWN;
- return retval;
- }
- isr_timed_out = ((timeval_ms() - t_start) > 500);
- } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
-
- /* Remove the temporary breakpoint */
- breakpoint_remove(target, pc_value);
-
- if (isr_timed_out) {
- LOG_DEBUG("Interrupt handlers didn't complete within time, "
- "leaving target running");
- } else {
- /* Step over next instruction with interrupts disabled */
- cortex_m3_write_debug_halt_mask(target,
- C_HALT | C_MASKINTS,
- 0);
+
+ /* Set a temporary break point */
+ if (breakpoint)
+ retval = cortex_m3_set_breakpoint(target, breakpoint);
+ else
+ retval = breakpoint_add(target, pc_value, 2, BKPT_TYPE_BY_ADDR(pc_value));
+ bool tmp_bp_set = (retval == ERROR_OK);
+
+ /* No more breakpoints left, just do a step */
+ if (!tmp_bp_set)
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
- /* Re-enable interrupts */
- cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+ else {
+ /* Start the core */
+ LOG_DEBUG("Starting core to serve pending interrupts");
+ int64_t t_start = timeval_ms();
+ cortex_m3_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
+
+ /* Wait for pending handlers to complete or timeout */
+ do {
+ retval = mem_ap_read_atomic_u32(swjdp,
+ DCB_DHCSR,
+ &cortex_m3->dcb_dhcsr);
+ if (retval != ERROR_OK) {
+ target->state = TARGET_UNKNOWN;
+ return retval;
+ }
+ isr_timed_out = ((timeval_ms() - t_start) > 500);
+ } while (!((cortex_m3->dcb_dhcsr & S_HALT) || isr_timed_out));
+
+ /* only remove breakpoint if we created it */
+ if (breakpoint)
+ cortex_m3_unset_breakpoint(target, breakpoint);
+ else {
+ /* Remove the temporary breakpoint */
+ breakpoint_remove(target, pc_value);
+ }
+
+ if (isr_timed_out) {
+ LOG_DEBUG("Interrupt handlers didn't complete within time, "
+ "leaving target running");
+ } else {
+ /* Step over next instruction with interrupts disabled */
+ cortex_m3_write_debug_halt_mask(target,
+ C_HALT | C_MASKINTS,
+ 0);
+ cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
+ /* Re-enable interrupts */
+ cortex_m3_write_debug_halt_mask(target, C_HALT, C_MASKINTS);
+ }
}
}
}
static int cortex_m3_assert_reset(struct target *target)
{
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
enum cortex_m3_soft_reset_config reset_config = cortex_m3->soft_reset_config;
LOG_DEBUG("target->state: %s",
return retval;
}
+ /* If the processor is sleeping in a WFI or WFE instruction, the
+ * C_HALT bit must be asserted to regain control */
+ if (cortex_m3->dcb_dhcsr & S_SLEEP) {
+ retval = mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
retval = mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
if (retval != ERROR_OK)
return retval;
if (reset_config == CORTEX_M3_RESET_VECTRESET) {
LOG_WARNING("Only resetting the Cortex-M3 core, use a reset-init event "
- "handler to reset any peripherals");
+ "handler to reset any peripherals or configure hardware srst support.");
}
{
{
int retval;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
int retval;
uint32_t reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
uint32_t size, uint32_t count, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
if (armv7m->arm.is_armv6m) {
uint32_t size, uint32_t count, const uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
if (armv7m->arm.is_armv6m) {
uint32_t cpuid, fpcr, mvfr0, mvfr1;
int i;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
- struct adiv5_dap *swjdp = &cortex_m3->armv7m.dap;
+ struct adiv5_dap *swjdp = cortex_m3->armv7m.arm.dap;
struct armv7m_common *armv7m = target_to_armv7m(target);
/* stlink shares the examine handler but does not support
uint32_t size, uint8_t *buffer)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
uint8_t data;
uint8_t ctrl;
uint32_t i;
if (!target_was_examined(target))
return ERROR_OK;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
if (!target->dbg_msg_enabled)
return ERROR_OK;
struct target *target = get_current_target(CMD_CTX);
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
- struct adiv5_dap *swjdp = &armv7m->dap;
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
uint32_t demcr = 0;
int retval;
projects / fw / openocd / blobdiff