target/cortex_m: fix cortex_m reset_config help and check for syntax error

[fw/openocd] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 03dc515729bacad85fae0177f06acf0e9a8f8019..4ce776cd0dd3193add842af303b82b34411cb7db 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -42,7 +42,7 @@
 
 /* NOTE:  most of this should work fine for the Cortex-M1 and
  * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
- * Some differences:  M0/M1 doesn't have FBP remapping or the
+ * Some differences:  M0/M1 doesn't have FPB remapping or the
  * DWT tracing/profiling support.  (So the cycle counter will
  * not be usable; the other stuff isn't currently used here.)
  *
@@ -165,7 +165,7 @@ static int cortex_m_single_step_core(struct target *target)
        struct armv7m_common *armv7m = &cortex_m->armv7m;
        int retval;
 
-       /* Mask interrupts before clearing halt, if done already.  This avoids
+       /* Mask interrupts before clearing halt, if not done already.  This avoids
         * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
         * HALT can put the core into an unknown state.
         */
@@ -237,8 +237,11 @@ static int cortex_m_endreset_event(struct target *target)
                        return retval;
        }
 
-       /* clear any interrupt masking */
-       cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
+       /* Restore proper interrupt masking setting. */
+       if (cortex_m->isrmasking_mode == CORTEX_M_ISRMASK_ON)
+               cortex_m_write_debug_halt_mask(target, C_MASKINTS, 0);
+       else
+               cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
 
        /* Enable features controlled by ITM and DWT blocks, and catch only
         * the vectors we were told to pay attention to.
@@ -252,7 +255,7 @@ static int cortex_m_endreset_event(struct target *target)
                return retval;
 
        /* Paranoia: evidently some (early?) chips don't preserve all the
-        * debug state (including FBP, DWT, etc) across reset...
+        * debug state (including FPB, DWT, etc) across reset...
         */
 
        /* Enable FPB */
@@ -1038,10 +1041,18 @@ static int cortex_m_assert_reset(struct target *target)
                retval = ERROR_OK;
        } else {
                /* Use a standard Cortex-M3 software reset mechanism.
-                * We default to using VECRESET as it is supported on all current cores.
+                * We default to using VECRESET as it is supported on all current cores
+                * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
                 * This has the disadvantage of not resetting the peripherals, so a
                 * reset-init event handler is needed to perform any peripheral resets.
                 */
+               if (!cortex_m->vectreset_supported
+                               && reset_config == CORTEX_M_RESET_VECTRESET) {
+                       reset_config = CORTEX_M_RESET_SYSRESETREQ;
+                       LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
+                       LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
+               }
+
                LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
                        ? "SYSRESETREQ" : "VECTRESET");
 
@@ -1274,7 +1285,7 @@ int cortex_m_remove_breakpoint(struct target *target, struct breakpoint *breakpo
 {
        struct cortex_m_common *cortex_m = target_to_cm(target);
 
-       /* REVISIT why check? FBP can be updated with core running ... */
+       /* REVISIT why check? FPB can be updated with core running ... */
        if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
@@ -1983,7 +1994,7 @@ int cortex_m_examine(struct target *target)
        /* stlink shares the examine handler but does not support
         * all its calls */
        if (!armv7m->stlink) {
-               if (cortex_m->apsel < 0) {
+               if (cortex_m->apsel == DP_APSEL_INVALID) {
                        /* Search for the MEM-AP */
                        retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
                        if (retval != ERROR_OK) {
@@ -2024,6 +2035,9 @@ int cortex_m_examine(struct target *target)
                }
                LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
+               /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
+               cortex_m->vectreset_supported = i > 1;
+
                if (i == 4) {
                        target_read_u32(target, MVFR0, &mvfr0);
                        target_read_u32(target, MVFR1, &mvfr1);
@@ -2415,8 +2429,16 @@ COMMAND_HANDLER(handle_cortex_m_reset_config_command)
        if (CMD_ARGC > 0) {
                if (strcmp(*CMD_ARGV, "sysresetreq") == 0)
                        cortex_m->soft_reset_config = CORTEX_M_RESET_SYSRESETREQ;
-               else if (strcmp(*CMD_ARGV, "vectreset") == 0)
-                       cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
+
+               else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
+                       if (target_was_examined(target)
+                                       && !cortex_m->vectreset_supported)
+                               LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
+                       else
+                               cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
+
+               } else
+                       return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        switch (cortex_m->soft_reset_config) {
@@ -2458,7 +2480,7 @@ static const struct command_registration cortex_m_exec_command_handlers[] = {
                .handler = handle_cortex_m_reset_config_command,
                .mode = COMMAND_ANY,
                .help = "configure software reset handling",
-               .usage = "['srst'|'sysresetreq'|'vectreset']",
+               .usage = "['sysresetreq'|'vectreset']",
        },
        COMMAND_REGISTRATION_DONE
 };