/* forward declarations */
static int cortex_m_store_core_reg_u32(struct target *target,
uint32_t num, uint32_t value);
+static void cortex_m_dwt_free(struct target *target);
-static int cortexm_dap_read_coreregister_u32(struct adiv5_dap *swjdp,
+static int cortexm_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum)
{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
uint32_t dcrdr;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
+ if (target->dbg_msg_enabled) {
+ retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
- retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
- if (retval != ERROR_OK)
- return retval;
-
- /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
- retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
- if (retval != ERROR_OK)
- return retval;
-
- /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
- retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_queue_ap_read(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
+ retval = mem_ap_write_u32(swjdp, DCB_DCRSR, regnum);
if (retval != ERROR_OK)
return retval;
- retval = dap_run(swjdp);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
- /* restore DCB_DCRDR - this needs to be in a seperate
- * transaction otherwise the emulated DCC channel breaks */
- if (retval == ERROR_OK)
- retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+ if (target->dbg_msg_enabled) {
+ /* restore DCB_DCRDR - this needs to be in a separate
+ * transaction otherwise the emulated DCC channel breaks */
+ if (retval == ERROR_OK)
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+ }
return retval;
}
-static int cortexm_dap_write_coreregister_u32(struct adiv5_dap *swjdp,
+static int cortexm_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum)
{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
int retval;
uint32_t dcrdr;
/* because the DCB_DCRDR is used for the emulated dcc channel
* we have to save/restore the DCB_DCRDR when used */
+ if (target->dbg_msg_enabled) {
+ retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
- retval = mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
- if (retval != ERROR_OK)
- return retval;
-
- /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
- retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
- if (retval != ERROR_OK)
- return retval;
-
- /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
- retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
- if (retval != ERROR_OK)
- return retval;
- retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
+ retval = mem_ap_write_u32(swjdp, DCB_DCRDR, value);
if (retval != ERROR_OK)
return retval;
- retval = dap_run(swjdp);
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRSR, regnum | DCRSR_WnR);
if (retval != ERROR_OK)
return retval;
- /* restore DCB_DCRDR - this needs to be in a seperate
- * transaction otherwise the emulated DCC channel breaks */
- if (retval == ERROR_OK)
- retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+ if (target->dbg_msg_enabled) {
+ /* restore DCB_DCRDR - this needs to be in a seperate
+ * transaction otherwise the emulated DCC channel breaks */
+ if (retval == ERROR_OK)
+ retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+ }
return retval;
}
return ERROR_OK;
}
+static int cortex_m_enable_fpb(struct target *target)
+{
+ int retval = target_write_u32(target, FP_CTRL, 3);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* check the fpb is actually enabled */
+ uint32_t fpctrl;
+ retval = target_read_u32(target, FP_CTRL, &fpctrl);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (fpctrl & 1)
+ return ERROR_OK;
+
+ return ERROR_FAIL;
+}
+
static int cortex_m_endreset_event(struct target *target)
{
int i;
*/
/* Enable FPB */
- retval = target_write_u32(target, FP_CTRL, 3);
- if (retval != ERROR_OK)
+ retval = cortex_m_enable_fpb(target);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to enable the FPB");
return retval;
+ }
cortex_m->fpb_enabled = 1;
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
arm_mode_name(arm->core_mode),
- *(uint32_t *)(arm->pc->value),
+ buf_get_u32(arm->pc->value, 0, 32),
target_state_name(target));
if (armv7m->post_debug_entry) {
}
if (cortex_m->dcb_dhcsr & S_RESET_ST) {
- /* check if still in reset */
- retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m->dcb_dhcsr);
- if (retval != ERROR_OK)
- return retval;
-
- if (cortex_m->dcb_dhcsr & S_RESET_ST) {
- target->state = TARGET_RESET;
- return ERROR_OK;
- }
+ target->state = TARGET_RESET;
+ return ERROR_OK;
}
if (target->state == TARGET_RESET) {
*/
LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
cortex_m->dcb_dhcsr);
- cortex_m_endreset_event(target);
+ retval = cortex_m_endreset_event(target);
+ if (retval != ERROR_OK) {
+ target->state = TARGET_UNKNOWN;
+ return retval;
+ }
target->state = TARGET_RUNNING;
prev_target_state = TARGET_RUNNING;
}
/* Single step past breakpoint at current address */
breakpoint = breakpoint_find(target, resume_pc);
if (breakpoint) {
- LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
+ LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %" PRIu32 ")",
breakpoint->address,
breakpoint->unique_id);
cortex_m_unset_breakpoint(target, breakpoint);
* This has the disadvantage of not resetting the peripherals, so a
* reset-init event handler is needed to perform any peripheral resets.
*/
- retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
- AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
- ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
- if (retval != ERROR_OK)
- return retval;
-
LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
? "SYSRESETREQ" : "VECTRESET");
"handler to reset any peripherals or configure hardware srst support.");
}
+ retval = mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+ AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
+ ? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
+ if (retval != ERROR_OK)
+ LOG_DEBUG("Ignoring AP write error right after reset");
+
+ retval = ahbap_debugport_init(swjdp);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("DP initialisation failed");
+ return retval;
+ }
+
{
/* I do not know why this is necessary, but it
* fixes strange effects (step/resume cause NMI
/* deassert reset lines */
adapter_deassert_reset();
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+ if ((jtag_reset_config & RESET_HAS_SRST) &&
+ !(jtag_reset_config & RESET_SRST_NO_GATING)) {
+ int retval = ahbap_debugport_init(target_to_cm(target)->armv7m.arm.dap);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("DP initialisation failed");
+ return retval;
+ }
+ }
+
return ERROR_OK;
}
struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
if (breakpoint->set) {
- LOG_WARNING("breakpoint (BPID: %d) already set", breakpoint->unique_id);
+ LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
return ERROR_OK;
}
comparator_list[fp_num].fpcr_value);
if (!cortex_m->fpb_enabled) {
LOG_DEBUG("FPB wasn't enabled, do it now");
- target_write_u32(target, FP_CTRL, 3);
+ retval = cortex_m_enable_fpb(target);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to enable the FPB");
+ return retval;
+ }
+
+ cortex_m->fpb_enabled = 1;
}
} else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
breakpoint->set = true;
}
- LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
+ LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
breakpoint->unique_id,
(int)(breakpoint->type),
breakpoint->address,
return ERROR_OK;
}
- LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
+ LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
breakpoint->unique_id,
(int)(breakpoint->type),
breakpoint->address,
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
+ if (breakpoint->length == 3) {
+ LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
+ breakpoint->length = 2;
+ }
+
if ((breakpoint->length != 2)) {
LOG_INFO("only breakpoints of two bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
uint32_t num, uint32_t *value)
{
int retval;
- struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = armv7m->arm.dap;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
switch (num) {
case 0 ... 18:
/* read a normal core register */
- retval = cortexm_dap_read_coreregister_u32(swjdp, value, num);
+ retval = cortexm_dap_read_coreregister_u32(target, value, num);
if (retval != ERROR_OK) {
LOG_ERROR("JTAG failure %i", retval);
LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
break;
+ case ARMV7M_FPSCR:
+ /* Floating-point Status and Registers */
+ retval = target_write_u32(target, DCB_DCRSR, 0x21);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_read_u32(target, DCB_DCRDR, value);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
+ break;
+
+ case ARMV7M_S0 ... ARMV7M_S31:
+ /* Floating-point Status and Registers */
+ retval = target_write_u32(target, DCB_DCRSR, num - ARMV7M_S0 + 0x40);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_read_u32(target, DCB_DCRDR, value);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
+ (int)(num - ARMV7M_S0), *value);
+ break;
+
case ARMV7M_PRIMASK:
case ARMV7M_BASEPRI:
case ARMV7M_FAULTMASK:
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
- cortexm_dap_read_coreregister_u32(swjdp, value, 20);
+ cortexm_dap_read_coreregister_u32(target, value, 20);
switch (num) {
case ARMV7M_PRIMASK:
int retval;
uint32_t reg;
struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = armv7m->arm.dap;
/* NOTE: we "know" here that the register identifiers used
* in the v7m header match the Cortex-M3 Debug Core Register
*/
switch (num) {
case 0 ... 18:
- retval = cortexm_dap_write_coreregister_u32(swjdp, value, num);
+ retval = cortexm_dap_write_coreregister_u32(target, value, num);
if (retval != ERROR_OK) {
struct reg *r;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
break;
+ case ARMV7M_FPSCR:
+ /* Floating-point Status and Registers */
+ retval = target_write_u32(target, DCB_DCRDR, value);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, DCB_DCRSR, 0x21 | (1<<16));
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
+ break;
+
+ case ARMV7M_S0 ... ARMV7M_S31:
+ /* Floating-point Status and Registers */
+ retval = target_write_u32(target, DCB_DCRDR, value);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, DCB_DCRSR, (num - ARMV7M_S0 + 0x40) | (1<<16));
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
+ (int)(num - ARMV7M_S0), value);
+ break;
+
case ARMV7M_PRIMASK:
case ARMV7M_BASEPRI:
case ARMV7M_FAULTMASK:
* in one Debug Core register. So say r0 and r2 docs;
* it was removed from r1 docs, but still works.
*/
- cortexm_dap_read_coreregister_u32(swjdp, ®, 20);
+ cortexm_dap_read_coreregister_u32(target, ®, 20);
switch (num) {
case ARMV7M_PRIMASK:
break;
}
- cortexm_dap_write_coreregister_u32(swjdp, reg, 20);
+ cortexm_dap_write_coreregister_u32(target, reg, 20);
LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
break;
return ERROR_OK;
}
+void cortex_m_deinit_target(struct target *target)
+{
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+
+ free(cortex_m->fp_comparator_list);
+ cortex_m_dwt_free(target);
+ free(cortex_m);
+}
+
/* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
* on r/w if the core is not running, and clear on resume or reset ... or
* at least, in a post_restore_context() method.
struct dwt_reg_state {
struct target *target;
uint32_t addr;
- uint32_t value; /* scratch/cache */
+ uint8_t value[4]; /* scratch/cache */
};
static int cortex_m_dwt_get_reg(struct reg *reg)
{
struct dwt_reg_state *state = reg->arch_info;
- return target_read_u32(state->target, state->addr, &state->value);
+ uint32_t tmp;
+ int retval = target_read_u32(state->target, state->addr, &tmp);
+ if (retval != ERROR_OK)
+ return retval;
+
+ buf_set_u32(state->value, 0, 32, tmp);
+ return ERROR_OK;
}
static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
r->name = d->name;
r->size = d->size;
- r->value = &state->value;
+ r->value = state->value;
r->arch_info = state;
r->type = &dwt_reg_type;
}
free(cm->dwt_comparator_list);
goto fail0;
}
- cache->name = "cortex-m3 dwt registers";
+ cache->name = "Cortex-M DWT registers";
cache->num_regs = 2 + cm->dwt_num_comp * 3;
cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
if (!cache->reg_list) {
*/
}
+static void cortex_m_dwt_free(struct target *target)
+{
+ struct cortex_m_common *cm = target_to_cm(target);
+ struct reg_cache *cache = cm->dwt_cache;
+
+ free(cm->dwt_comparator_list);
+ cm->dwt_comparator_list = NULL;
+
+ if (cache) {
+ register_unlink_cache(&target->reg_cache, cache);
+
+ if (cache->reg_list) {
+ for (size_t i = 0; i < cache->num_regs; i++)
+ free(cache->reg_list[i].arch_info);
+ free(cache->reg_list);
+ }
+ free(cache);
+ }
+ cm->dwt_cache = NULL;
+}
+
#define MVFR0 0xe000ef40
#define MVFR1 0xe000ef44
armv7m->arm.is_armv6m = true;
}
+ if (armv7m->fp_feature != FPv4_SP &&
+ armv7m->arm.core_cache->num_regs > ARMV7M_NUM_CORE_REGS_NOFP) {
+ /* free unavailable FPU registers */
+ size_t idx;
+ for (idx = ARMV7M_NUM_CORE_REGS_NOFP;
+ idx < armv7m->arm.core_cache->num_regs;
+ idx++)
+ free(armv7m->arm.core_cache->reg_list[idx].value);
+ armv7m->arm.core_cache->num_regs = ARMV7M_NUM_CORE_REGS_NOFP;
+ }
+
if (i == 4 || i == 3) {
/* Cortex-M3/M4 has 4096 bytes autoincrement range */
armv7m->dap.tar_autoincr_block = (1 << 12);
}
+ /* Configure trace modules */
+ retval = target_write_u32(target, DCB_DEMCR, TRCENA | armv7m->demcr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (armv7m->trace_config.config_type != DISABLED) {
+ armv7m_trace_tpiu_config(target);
+ armv7m_trace_itm_config(target);
+ }
+
/* NOTE: FPB and DWT are both optional. */
/* Setup FPB */
cortex_m->fp_num_code = ((fpcr >> 8) & 0x70) | ((fpcr >> 4) & 0xF);
cortex_m->fp_num_lit = (fpcr >> 8) & 0xF;
cortex_m->fp_code_available = cortex_m->fp_num_code;
+ free(cortex_m->fp_comparator_list);
cortex_m->fp_comparator_list = calloc(
cortex_m->fp_num_code + cortex_m->fp_num_lit,
sizeof(struct cortex_m_fp_comparator));
cortex_m->fp_num_lit);
/* Setup DWT */
+ cortex_m_dwt_free(target);
cortex_m_dwt_setup(cortex_m, target);
/* These hardware breakpoints only work for code in flash! */
return ERROR_OK;
}
-static int cortex_m_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctrl)
{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct adiv5_dap *swjdp = armv7m->arm.dap;
uint16_t dcrdr;
+ uint8_t buf[2];
int retval;
- mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR);
+ retval = mem_ap_read(swjdp, buf, 2, 1, DCB_DCRDR, false);
+ if (retval != ERROR_OK)
+ return retval;
+
+ dcrdr = target_buffer_get_u16(target, buf);
*ctrl = (uint8_t)dcrdr;
*value = (uint8_t)(dcrdr >> 8);
/* write ack back to software dcc register
* signify we have read data */
if (dcrdr & (1 << 0)) {
- dcrdr = 0;
- retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR);
+ target_buffer_set_u16(target, buf, 0);
+ retval = mem_ap_write(swjdp, buf, 2, 1, DCB_DCRDR, false);
if (retval != ERROR_OK)
return retval;
}
static int cortex_m_target_request_data(struct target *target,
uint32_t size, uint8_t *buffer)
{
- struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = armv7m->arm.dap;
uint8_t data;
uint8_t ctrl;
uint32_t i;
for (i = 0; i < (size * 4); i++) {
- cortex_m_dcc_read(swjdp, &data, &ctrl);
+ int retval = cortex_m_dcc_read(target, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
buffer[i] = data;
}
struct target *target = priv;
if (!target_was_examined(target))
return ERROR_OK;
- struct armv7m_common *armv7m = target_to_armv7m(target);
- struct adiv5_dap *swjdp = armv7m->arm.dap;
if (!target->dbg_msg_enabled)
return ERROR_OK;
if (target->state == TARGET_RUNNING) {
uint8_t data;
uint8_t ctrl;
+ int retval;
- cortex_m_dcc_read(swjdp, &data, &ctrl);
+ retval = cortex_m_dcc_read(target, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
/* check if we have data */
if (ctrl & (1 << 0)) {
/* we assume target is quick enough */
request = data;
- cortex_m_dcc_read(swjdp, &data, &ctrl);
- request |= (data << 8);
- cortex_m_dcc_read(swjdp, &data, &ctrl);
- request |= (data << 16);
- cortex_m_dcc_read(swjdp, &data, &ctrl);
- request |= (data << 24);
+ for (int i = 1; i <= 3; i++) {
+ retval = cortex_m_dcc_read(target, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
+ request |= ((uint32_t)data << (i * 8));
+ }
target_request(target, request);
}
}
{
.chain = armv7m_command_handlers,
},
+ {
+ .chain = armv7m_trace_command_handlers,
+ },
{
.name = "cortex_m",
.mode = COMMAND_EXEC,
.target_create = cortex_m_target_create,
.init_target = cortex_m_init_target,
.examine = cortex_m_examine,
+ .deinit_target = cortex_m_deinit_target,
};
projects / fw / openocd / blobdiff