target->debug_reason = DBG_REASON_WATCHPOINT;
else if (cortex_m->nvic_dfsr & DFSR_VCATCH)
target->debug_reason = DBG_REASON_BREAKPOINT;
- else /* EXTERNAL, HALTED */
+ else if (cortex_m->nvic_dfsr & DFSR_EXTERNAL)
+ target->debug_reason = DBG_REASON_DBGRQ;
+ else /* HALTED */
target->debug_reason = DBG_REASON_UNDEFINED;
}
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
- /* soft_reset_halt is deprecated on cortex_m as the same functionality
- * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'
- * As this reset only used VC_CORERESET it would only ever reset the cortex_m
+ /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
+ * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
+ * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
* core, not the peripherals */
- LOG_WARNING("soft_reset_halt is deprecated, please use 'reset halt' instead.");
+ LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
+
+ /* Set C_DEBUGEN */
+ retval = cortex_m_write_debug_halt_mask(target, 0, C_STEP | C_MASKINTS);
+ if (retval != ERROR_OK)
+ return retval;
/* Enter debug state on reset; restore DEMCR in endreset_event() */
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
* a normal step, otherwise we have to manually step over the bkpt
* instruction - as such simulate a step */
if (bkpt_inst_found == false) {
- if ((cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO)) {
+ if (cortex_m->isrmasking_mode != CORTEX_M_ISRMASK_AUTO) {
/* Automatic ISR masking mode off: Just step over the next
* instruction, with interrupts on or off as appropriate. */
cortex_m_set_maskints_for_step(target);
}
target->state = TARGET_RESET;
- jtag_add_sleep(50000);
+ jtag_sleep(50000);
register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
int cortex_m_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int dwt_num = 0;
- uint32_t mask, temp;
struct cortex_m_common *cortex_m = target_to_cm(target);
- /* watchpoint params were validated earlier */
- mask = 0;
- temp = watchpoint->length;
- while (temp) {
- temp >>= 1;
- mask++;
- }
- mask--;
-
/* REVISIT Don't fully trust these "not used" records ... users
* may set up breakpoints by hand, e.g. dual-address data value
* watchpoint using comparator #1; comparator #0 matching cycle
target_write_u32(target, comparator->dwt_comparator_address + 0,
comparator->comp);
- comparator->mask = mask;
- target_write_u32(target, comparator->dwt_comparator_address + 4,
- comparator->mask);
+ if ((cortex_m->dwt_devarch & 0x1FFFFF) != DWT_DEVARCH_ARMV8M) {
+ uint32_t mask = 0, temp;
+
+ /* watchpoint params were validated earlier */
+ temp = watchpoint->length;
+ while (temp) {
+ temp >>= 1;
+ mask++;
+ }
+ mask--;
+
+ comparator->mask = mask;
+ target_write_u32(target, comparator->dwt_comparator_address + 4,
+ comparator->mask);
- switch (watchpoint->rw) {
+ switch (watchpoint->rw) {
case WPT_READ:
comparator->function = 5;
break;
case WPT_ACCESS:
comparator->function = 7;
break;
+ }
+ } else {
+ uint32_t data_size = watchpoint->length >> 1;
+ comparator->mask = (watchpoint->length >> 1) | 1;
+
+ switch (watchpoint->rw) {
+ case WPT_ACCESS:
+ comparator->function = 4;
+ break;
+ case WPT_WRITE:
+ comparator->function = 5;
+ break;
+ case WPT_READ:
+ comparator->function = 6;
+ break;
+ }
+ comparator->function = comparator->function | (1 << 4) |
+ (data_size << 10);
}
+
target_write_u32(target, comparator->dwt_comparator_address + 8,
comparator->function);
{
struct dwt_reg_state *state;
- state = calloc(1, sizeof *state);
+ state = calloc(1, sizeof(*state));
if (!state)
return;
state->addr = d->addr;
return;
}
+ target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
+ LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
+
cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
cm->dwt_comp_available = cm->dwt_num_comp;
cm->dwt_comparator_list = calloc(cm->dwt_num_comp,
return;
}
- cache = calloc(1, sizeof *cache);
+ cache = calloc(1, sizeof(*cache));
if (!cache) {
fail1:
free(cm->dwt_comparator_list);
}
cache->name = "Cortex-M DWT registers";
cache->num_regs = 2 + cm->dwt_num_comp * 3;
- cache->reg_list = calloc(cache->num_regs, sizeof *cache->reg_list);
+ cache->reg_list = calloc(cache->num_regs, sizeof(*cache->reg_list));
if (!cache->reg_list) {
free(cache);
goto fail1;
#define MVFR1_DEFAULT_M7_SP 0x11000011
#define MVFR1_DEFAULT_M7_DP 0x12000011
+static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
+ struct adiv5_ap **debug_ap)
+{
+ if (dap_find_ap(swjdp, AP_TYPE_AHB3_AP, debug_ap) == ERROR_OK)
+ return ERROR_OK;
+
+ return dap_find_ap(swjdp, AP_TYPE_AHB5_AP, debug_ap);
+}
+
int cortex_m_examine(struct target *target)
{
int retval;
if (!armv7m->stlink) {
if (cortex_m->apsel == DP_APSEL_INVALID) {
/* Search for the MEM-AP */
- retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7m->debug_ap);
+ retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
if (retval != ERROR_OK) {
LOG_ERROR("Could not find MEM-AP to control the core");
return retval;
/* Get CPU Type */
i = (cpuid >> 4) & 0xf;
+ switch (cpuid & ARM_CPUID_PARTNO_MASK) {
+ case CORTEX_M23_PARTNO:
+ i = 23;
+ break;
+
+ case CORTEX_M33_PARTNO:
+ i = 33;
+ break;
+
+ default:
+ break;
+ }
+
+
LOG_DEBUG("Cortex-M%d r%" PRId8 "p%" PRId8 " processor detected",
i, (uint8_t)((cpuid >> 20) & 0xf), (uint8_t)((cpuid >> 0) & 0xf));
cortex_m->maskints_erratum = false;
LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
armv7m->fp_feature = FPv4_SP;
}
- } else if (i == 7) {
+ } else if (i == 7 || i == 33) {
target_read_u32(target, MVFR0, &mvfr0);
target_read_u32(target, MVFR1, &mvfr1);
/*--------------------------------------------------------------------------*/
-static int cortex_m_verify_pointer(struct command_context *cmd_ctx,
+static int cortex_m_verify_pointer(struct command_invocation *cmd,
struct cortex_m_common *cm)
{
if (cm->common_magic != CORTEX_M_COMMON_MAGIC) {
- command_print(cmd_ctx, "target is not a Cortex-M");
+ command_print(cmd, "target is not a Cortex-M");
return ERROR_TARGET_INVALID;
}
return ERROR_OK;
{ "reset", VC_CORERESET, },
};
- retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
+ retval = cortex_m_verify_pointer(CMD, cortex_m);
if (retval != ERROR_OK)
return retval;
}
for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
- command_print(CMD_CTX, "%9s: %s", vec_ids[i].name,
+ command_print(CMD, "%9s: %s", vec_ids[i].name,
(demcr & vec_ids[i].mask) ? "catch" : "ignore");
}
const Jim_Nvp *n;
- retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
+ retval = cortex_m_verify_pointer(CMD, cortex_m);
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED) {
- command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+ command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
}
n = Jim_Nvp_value2name_simple(nvp_maskisr_modes, cortex_m->isrmasking_mode);
- command_print(CMD_CTX, "cortex_m interrupt mask %s", n->name);
+ command_print(CMD, "cortex_m interrupt mask %s", n->name);
return ERROR_OK;
}
int retval;
char *reset_config;
- retval = cortex_m_verify_pointer(CMD_CTX, cortex_m);
+ retval = cortex_m_verify_pointer(CMD, cortex_m);
if (retval != ERROR_OK)
return retval;
break;
}
- command_print(CMD_CTX, "cortex_m reset_config %s", reset_config);
+ command_print(CMD, "cortex_m reset_config %s", reset_config);
return ERROR_OK;
}
projects / fw / openocd / blobdiff