cortex_m: mem_ap access functions take number of bytes, not words

[fw/openocd] / src / target / cortex_m.c

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index fbe635bdd8bc695bfe90b49f5e27cd4389179c49..10a77d5fd862546040b8bc94e53edb18aed27164 100644 (file)
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -433,17 +433,6 @@ static int cortex_m3_debug_entry(struct target *target)
        r = arm->cpsr;
        xPSR = buf_get_u32(r->value, 0, 32);
 
-#ifdef ARMV7_GDB_HACKS
-       /* FIXME this breaks on scan chains with more than one Cortex-M3.
-        * Instead, each CM3 should have its own dummy value...
-        */
-       /* copy real xpsr reg for gdb, setting thumb bit */
-       buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
-       buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
-       armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
-       armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
-#endif
-
        /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
        if (xPSR & 0xf00) {
                r->dirty = r->valid;
@@ -1232,17 +1221,8 @@ int cortex_m3_add_breakpoint(struct target *target, struct breakpoint *breakpoin
 {
        struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
 
-       if (cortex_m3->auto_bp_type) {
+       if (cortex_m3->auto_bp_type)
                breakpoint->type = BKPT_TYPE_BY_ADDR(breakpoint->address);
-#ifdef ARMV7_GDB_HACKS
-               if (breakpoint->length != 2) {
-                       /* XXX Hack: Replace all breakpoints with length != 2 with
-                        * a hardware breakpoint. */
-                       breakpoint->type = BKPT_HARD;
-                       breakpoint->length = 2;
-               }
-#endif
-       }
 
        if (breakpoint->type != BKPT_TYPE_BY_ADDR(breakpoint->address)) {
                if (breakpoint->type == BKPT_HARD) {
@@ -1540,18 +1520,6 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
        struct armv7m_common *armv7m = target_to_armv7m(target);
        struct adiv5_dap *swjdp = armv7m->arm.dap;
 
-#ifdef ARMV7_GDB_HACKS
-       /* If the LR register is being modified, make sure it will put us
-        * in "thumb" mode, or an INVSTATE exception will occur. This is a
-        * hack to deal with the fact that gdb will sometimes "forge"
-        * return addresses, and doesn't set the LSB correctly (i.e., when
-        * printing expressions containing function calls, it sets LR = 0.)
-        * Valid exception return codes have bit 0 set too.
-        */
-       if (num == ARMV7M_R14)
-               value |= 0x01;
-#endif
-
        /* NOTE:  we "know" here that the register identifiers used
         * in the v7m header match the Cortex-M3 Debug Core Register
         * Selector values for R0..R15, xPSR, MSP, and PSP.
@@ -1924,7 +1892,7 @@ static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *
        uint16_t dcrdr;
        int retval;
 
-       mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
+       mem_ap_read_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR);
        *ctrl = (uint8_t)dcrdr;
        *value = (uint8_t)(dcrdr >> 8);
 
@@ -1934,7 +1902,7 @@ static int cortex_m3_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *
         * signify we have read data */
        if (dcrdr & (1 << 0)) {
                dcrdr = 0;
-               retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 1, DCB_DCRDR);
+               retval = mem_ap_write_buf_u16(swjdp, (uint8_t *)&dcrdr, 2, DCB_DCRDR);
                if (retval != ERROR_OK)
                        return retval;
        }