if (retval != ERROR_OK)
return retval;
retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
- // XXX check retval
+ if (retval != ERROR_OK)
+ return retval;
/* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
if (retval != ERROR_OK)
return retval;
retval = dap_queue_ap_write(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
- // XXX check retval
+ if (retval != ERROR_OK)
+ return retval;
retval = dap_run(swjdp);
+ if (retval != ERROR_OK)
+ return retval;
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
static int cortex_m3_examine_exception_reason(struct target *target)
{
- uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
+ uint32_t shcsr = 0, except_sr = 0, cfsr = -1, except_ar = -1;
struct armv7m_common *armv7m = target_to_armv7m(target);
struct adiv5_dap *swjdp = &armv7m->dap;
int retval;