#define CPUDBG_BVR_BASE 0x100
#define CPUDBG_BCR_BASE 0x140
#define CPUDBG_WVR_BASE 0x180
+#define CPUDBG_WCR_BASE 0x1C0
#define CPUDBG_OSLAR 0x300
#define CPUDBG_OSLSR 0x304
#define DSCR_MON_DBG_MODE 15
#define DSCR_INSTR_COMP 24
#define DSCR_DTR_TX_FULL 29
+#define DSCR_DTR_RX_FULL 30
-typedef struct cortex_a8_brp_s
+struct cortex_a8_brp
{
int used;
int type;
uint32_t value;
uint32_t control;
uint8_t BRPn;
-} cortex_a8_brp_t;
+};
-typedef struct cortex_a8_wrp_s
+struct cortex_a8_wrp
{
int used;
int type;
uint32_t value;
uint32_t control;
uint8_t WRPn;
-} cortex_a8_wrp_t;
+};
-typedef struct cortex_a8_common_s
+struct cortex_a8_common
{
int common_magic;
- arm_jtag_t jtag_info;
+ struct arm_jtag jtag_info;
/* Context information */
uint32_t cpudbg_dscr;
int brp_num;
int brp_num_available;
// int brp_enabled;
- cortex_a8_brp_t *brp_list;
+ struct cortex_a8_brp *brp_list;
/* Watchpoint register pairs */
int wrp_num;
int wrp_num_available;
- cortex_a8_wrp_t *wrp_list;
+ struct cortex_a8_wrp *wrp_list;
/* Interrupts */
int intlinesnum;
/* Use cortex_a8_read_regs_through_mem for fast register reads */
int fast_reg_read;
- armv7a_common_t armv7a_common;
- void *arch_info;
-} cortex_a8_common_t;
+ struct armv7a_common armv7a_common;
+};
-extern int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap);
-int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+static inline struct cortex_a8_common *
+target_to_cortex_a8(struct target *target)
+{
+ return container_of(target->arch_info, struct cortex_a8_common,
+ armv7a_common.armv4_5_common);
+}
+
+int cortex_a8_init_arch_info(struct target *target,
+ struct cortex_a8_common *cortex_a8, struct jtag_tap *tap);
#endif /* CORTEX_A8_H */