reg_arch_type_t -> struct reg_arch_type

[fw/openocd] / src / target / cortex_a8.h

diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h
index c1610d540e7fdbf78690371d04400f99c2e84634..131cddbf9138839c8f086d3a8137eb7eb184a016 100644 (file)
--- a/src/target/cortex_a8.h
+++ b/src/target/cortex_a8.h
@@ -42,6 +42,8 @@ extern char* cortex_a8_state_strings[];
 /* Debug Control Block */
 #define CPUDBG_DIDR            0x000
 #define CPUDBG_WFAR            0x018
+#define CPUDBG_VCR     0x01C
+#define CPUDBG_ECR     0x024
 #define CPUDBG_DSCCR   0x028
 #define CPUDBG_DTRRX   0x080
 #define CPUDBG_ITR     0x084
@@ -51,14 +53,35 @@ extern char* cortex_a8_state_strings[];
 #define CPUDBG_BVR_BASE        0x100
 #define CPUDBG_BCR_BASE        0x140
 #define CPUDBG_WVR_BASE        0x180
+#define CPUDBG_WCR_BASE        0x1C0
+
+#define CPUDBG_OSLAR   0x300
+#define CPUDBG_OSLSR   0x304
+#define CPUDBG_OSSRR   0x308
+
+#define CPUDBG_PRCR    0x310
+#define CPUDBG_PRSR    0x314
 
 #define CPUDBG_CPUID   0xD00
 #define CPUDBG_CTYPR   0xD04
 #define CPUDBG_TTYPR   0xD0C
+#define CPUDBG_LOCKACCESS 0xFB0
+#define CPUDBG_LOCKSTATUS 0xFB4
+#define CPUDBG_AUTHSTATUS 0xFB8
 
 #define BRP_NORMAL 0
 #define BRP_CONTEXT 1
 
+/* DSCR Bit offset */
+#define DSCR_CORE_HALTED               0
+#define DSCR_CORE_RESTARTED    1
+#define DSCR_EXT_INT_EN                13
+#define DSCR_HALT_DBG_MODE             14
+#define DSCR_MON_DBG_MODE              15
+#define DSCR_INSTR_COMP                24
+#define DSCR_DTR_TX_FULL               29
+#define DSCR_DTR_RX_FULL               30
+
 typedef struct  cortex_a8_brp_s
 {
        int used;
@@ -77,15 +100,10 @@ typedef struct  cortex_a8_wrp_s
        uint8_t         WRPn;
 } cortex_a8_wrp_t;
 
-typedef struct cortex_a8_common_s
+struct cortex_a8_common
 {
        int common_magic;
-       arm_jtag_t jtag_info;
-
-       /* Core Debug Unit */
-       uint32_t debug_base;
-       uint8_t debug_ap;
-       uint8_t memory_ap;
+       struct arm_jtag jtag_info;
 
        /* Context information */
        uint32_t cpudbg_dscr;
@@ -115,12 +133,17 @@ typedef struct cortex_a8_common_s
        /* Use cortex_a8_read_regs_through_mem for fast register reads */
        int fast_reg_read;
 
-       armv7a_common_t armv7a_common;
-       void *arch_info;
-} cortex_a8_common_t;
+       struct armv7a_common armv7a_common;
+};
+
+static inline struct cortex_a8_common *
+target_to_cortex_a8(struct target_s *target)
+{
+       return container_of(target->arch_info, struct cortex_a8_common,
+                       armv7a_common.armv4_5_common);
+}
 
-extern int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap);
-int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int cortex_a8_init_arch_info(target_t *target,
+               struct cortex_a8_common *cortex_a8, struct jtag_tap *tap);
 
 #endif /* CORTEX_A8_H */