#include "register.h"
#include "target_request.h"
#include "target_type.h"
+#include "arm_opcodes.h"
static int cortex_a8_poll(struct target *target);
static int cortex_a8_debug_entry(struct target *target);
-static int cortex_a8_restore_context(struct target *target);
+static int cortex_a8_restore_context(struct target *target, bool bpwp);
static int cortex_a8_set_breakpoint(struct target *target,
struct breakpoint *breakpoint, uint8_t matchmode);
static int cortex_a8_unset_breakpoint(struct target *target,
uint32_t *value, int regnum);
static int cortex_a8_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum);
+static int cortex_a8_mmu(struct target *target, int *enabled);
+static int cortex_a8_virt2phys(struct target *target,
+ uint32_t virt, uint32_t *phys);
+static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
+ int d_u_cache, int i_cache);
+static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
+ int d_u_cache, int i_cache);
+static uint32_t cortex_a8_get_ttb(struct target *target);
+
+
/*
* FIXME do topology discovery using the ROM; don't
- * assume this is an OMAP3.
+ * assume this is an OMAP3. Also, allow for multiple ARMv7-A
+ * cores, with different AP numbering ... don't use a #define
+ * for these numbers, use per-core armv7a state.
*/
#define swjdp_memoryap 0
#define swjdp_debugap 1
static int cortex_a8_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
int retval;
uint32_t dummy;
/* To reduce needless round-trips, pass in a pointer to the current
* DSCR value. Initialize it to zero if you just need to know the
- * value on return from this function; or (1 << DSCR_INSTR_COMP) if
- * you happen to know that no instruction is pending.
+ * value on return from this function; or DSCR_INSTR_COMP if you
+ * happen to know that no instruction is pending.
*/
static int cortex_a8_exec_opcode(struct target *target,
uint32_t opcode, uint32_t *dscr_p)
uint32_t dscr;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
dscr = dscr_p ? *dscr_p : 0;
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
/* Wait for InstrCompl bit to be set */
- while ((dscr & (1 << DSCR_INSTR_COMP)) == 0)
+ while ((dscr & DSCR_INSTR_COMP) == 0)
{
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
return retval;
}
}
- while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
+ while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
if (dscr_p)
*dscr_p = dscr;
{
int retval = ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
cortex_a8_dap_write_coreregister_u32(target, address, 0);
uint8_t reg = regnum&0xFF;
uint32_t dscr = 0;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
if (reg > 17)
return retval;
}
/* Wait for DTRRXfull then read DTRRTX */
- while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0)
+ while ((dscr & DSCR_DTR_TX_FULL) == 0)
{
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
uint8_t Rd = regnum&0xFF;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- if (dscr & (1 << DSCR_DTR_RX_FULL))
+ if (dscr & DSCR_DTR_RX_FULL)
{
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
retval = mem_ap_write_atomic_u32(swjdp, address, value);
static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
- return mem_ap_write_u32(&a8->armv7a_common.swjdp_info,
+ return mem_ap_write_u32(&a8->armv7a_common.dap,
a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
uint32_t *dscr_p)
{
- struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ struct adiv5_dap *swjdp = &a8->armv7a_common.dap;
+ uint32_t dscr = DSCR_INSTR_COMP;
int retval;
if (dscr_p)
dscr = *dscr_p;
/* Wait for DTRRXfull */
- while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) {
+ while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
+ struct adiv5_dap *swjdp = &a8->armv7a_common.dap;
uint32_t dscr;
int retval;
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
- } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0);
+ } while ((dscr & DSCR_INSTR_COMP) == 0);
/* this "should never happen" ... */
- if (dscr & (1 << DSCR_DTR_RX_FULL)) {
+ if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
retval = cortex_a8_exec_opcode(
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
int retval;
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
retval = cortex_a8_write_dcc(a8, data);
uint32_t opcode, uint32_t data)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
int retval;
retval = cortex_a8_write_dcc(a8, data);
static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
{
struct target *target = dpm->arm->target;
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
/* "Prefetch flush" after modifying execution status in CPSR */
return cortex_a8_exec_opcode(target,
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
int retval;
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
/* the opcode, writing data to DCC */
retval = cortex_a8_exec_opcode(
uint32_t opcode, uint32_t *data)
{
struct cortex_a8_common *a8 = dpm_to_a8(dpm);
- uint32_t dscr = 1 << DSCR_INSTR_COMP;
+ uint32_t dscr = DSCR_INSTR_COMP;
int retval;
/* the opcode, writing data to R0 */
return cortex_a8_read_dcc(a8, data, &dscr);
}
+static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index,
+ uint32_t addr, uint32_t control)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t vr = a8->armv7a_common.debug_base;
+ uint32_t cr = a8->armv7a_common.debug_base;
+ int retval;
+
+ switch (index) {
+ case 0 ... 15: /* breakpoints */
+ vr += CPUDBG_BVR_BASE;
+ cr += CPUDBG_BCR_BASE;
+ break;
+ case 16 ... 31: /* watchpoints */
+ vr += CPUDBG_WVR_BASE;
+ cr += CPUDBG_WCR_BASE;
+ index -= 16;
+ break;
+ default:
+ return ERROR_FAIL;
+ }
+ vr += 4 * index;
+ cr += 4 * index;
+
+ LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
+ (unsigned) vr, (unsigned) cr);
+
+ retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ vr, addr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ cr, control);
+ return retval;
+}
+
+static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t cr;
+
+ switch (index) {
+ case 0 ... 15:
+ cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
+ break;
+ case 16 ... 31:
+ cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
+ index -= 16;
+ break;
+ default:
+ return ERROR_FAIL;
+ }
+ cr += 4 * index;
+
+ LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
+
+ /* clear control register */
+ return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
+}
+
static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
{
struct arm_dpm *dpm = &a8->armv7a_common.dpm;
+ int retval;
dpm->arm = &a8->armv7a_common.armv4_5_common;
dpm->didr = didr;
dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
- return arm_dpm_setup(dpm);
+ dpm->bpwp_enable = cortex_a8_bpwp_enable;
+ dpm->bpwp_disable = cortex_a8_bpwp_disable;
+
+ retval = arm_dpm_setup(dpm);
+ if (retval == ERROR_OK)
+ retval = arm_dpm_initialize(dpm);
+
+ return retval;
}
uint32_t dscr;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
enum target_state prev_target_state = target->state;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
int retval = ERROR_OK;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
dap_ap_select(swjdp, swjdp_debugap);
*/
mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
retval = mem_ap_write_atomic_u32(swjdp,
- armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+ armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
if (retval != ERROR_OK)
goto out;
do {
mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
+ } while ((dscr & DSCR_CORE_HALTED) == 0);
target->debug_reason = DBG_REASON_DBGRQ;
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
// struct breakpoint *breakpoint = NULL;
uint32_t resume_pc, dscr;
dap_ap_select(swjdp, swjdp_debugap);
if (!debug_execution)
- {
target_free_all_working_areas(target);
-// cortex_m3_enable_breakpoints(target);
-// cortex_m3_enable_watchpoints(target);
- }
#if 0
if (debug_execution)
#endif
/* current = 1: continue on current pc, otherwise continue at <address> */
- resume_pc = buf_get_u32(
- armv4_5->core_cache->reg_list[15].value,
- 0, 32);
+ resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32);
if (!current)
resume_pc = address;
*/
switch (armv4_5->core_state)
{
- case ARMV4_5_STATE_ARM:
+ case ARM_STATE_ARM:
resume_pc &= 0xFFFFFFFC;
break;
- case ARMV4_5_STATE_THUMB:
+ case ARM_STATE_THUMB:
case ARM_STATE_THUMB_EE:
/* When the return address is loaded into PC
* bit 0 must be 1 to stay in Thumb state
*/
resume_pc |= 0x1;
break;
- case ARMV4_5_STATE_JAZELLE:
+ case ARM_STATE_JAZELLE:
LOG_ERROR("How do I resume into Jazelle state??");
return ERROR_FAIL;
}
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
- buf_set_u32(armv4_5->core_cache->reg_list[15].value,
- 0, 32, resume_pc);
- armv4_5->core_cache->reg_list[15].dirty = 1;
- armv4_5->core_cache->reg_list[15].valid = 1;
+ buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc);
+ armv4_5->pc->dirty = 1;
+ armv4_5->pc->valid = 1;
- cortex_a8_restore_context(target);
+ cortex_a8_restore_context(target, handle_breakpoints);
#if 0
/* the front-end may request us not to handle breakpoints */
}
#endif
- /* Restart core and wait for it to be started */
+ /* Restart core and wait for it to be started
+ * NOTE: this clears DSCR_ITR_EN and other bits.
+ *
+ * REVISIT: for single stepping, we probably want to
+ * disable IRQs by default, with optional override...
+ */
mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
do {
mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
+ } while ((dscr & DSCR_CORE_RESTARTED) == 0);
target->debug_reason = DBG_REASON_NOTHALTED;
target->state = TARGET_RUNNING;
static int cortex_a8_debug_entry(struct target *target)
{
int i;
- uint32_t regfile[16], pc, cpsr, dscr;
+ uint32_t regfile[16], cpsr, dscr;
int retval = ERROR_OK;
struct working_area *regfile_working_area = NULL;
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
struct reg *reg;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
- /* Enable the ITR execution once we are in debug mode */
+ /* REVISIT surely we should not re-read DSCR !! */
mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
* Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
*/
- dscr |= (1 << DSCR_EXT_INT_EN);
+ /* Enable the ITR execution once we are in debug mode */
+ dscr |= DSCR_ITR_EN;
retval = mem_ap_write_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, dscr);
/* Examine debug reason */
- switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
- {
- case 0: /* DRCR[0] write */
- case 4: /* EDBGRQ */
- target->debug_reason = DBG_REASON_DBGRQ;
- break;
- case 1: /* HW breakpoint */
- case 3: /* SW BKPT */
- case 5: /* vector catch */
- target->debug_reason = DBG_REASON_BREAKPOINT;
- break;
- case 10: /* precise watchpoint */
- target->debug_reason = DBG_REASON_WATCHPOINT;
- /* REVISIT could collect WFAR later, to see just
- * which instruction triggered the watchpoint.
- */
- break;
- default:
- target->debug_reason = DBG_REASON_UNDEFINED;
- break;
+ arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
+
+ /* save address of instruction that triggered the watchpoint? */
+ if (target->debug_reason == DBG_REASON_WATCHPOINT) {
+ uint32_t wfar;
+
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_WFAR,
+ &wfar);
+ arm_dpm_report_wfar(&armv7a->dpm, wfar);
}
/* REVISIT fast_reg_read is never set ... */
/* read Current PSR */
cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
- pc = regfile[15];
dap_ap_select(swjdp, swjdp_debugap);
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
regfile[ARM_PC] -= 8;
}
- reg = armv4_5->core_cache->reg_list + 15;
+ reg = armv4_5->pc;
buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
reg->dirty = reg->valid;
}
if (armv7a->post_debug_entry)
armv7a->post_debug_entry(target);
-
-
return retval;
-
}
static void cortex_a8_post_debug_entry(struct target *target)
}
/* current = 1: continue on current pc, otherwise continue at <address> */
- r = armv4_5->core_cache->reg_list + 15;
+ r = armv4_5->pc;
if (!current)
{
buf_set_u32(r->value, 0, 32, address);
/* Setup single step breakpoint */
stepbreakpoint.address = address;
- stepbreakpoint.length = (armv4_5->core_state == ARMV4_5_STATE_THUMB)
+ stepbreakpoint.length = (armv4_5->core_state == ARM_STATE_THUMB)
? 2 : 4;
stepbreakpoint.type = BKPT_HARD;
stepbreakpoint.set = 0;
}
cortex_a8_unset_breakpoint(target, &stepbreakpoint);
- if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
+ if (timeout > 0)
+ target->debug_reason = DBG_REASON_BREAKPOINT;
if (breakpoint)
cortex_a8_set_breakpoint(target, breakpoint, 0);
return ERROR_OK;
}
-static int cortex_a8_restore_context(struct target *target)
+static int cortex_a8_restore_context(struct target *target, bool bpwp)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
if (armv7a->pre_restore_context)
armv7a->pre_restore_context(target);
- arm_dpm_write_dirty_registers(&armv7a->dpm);
-
- if (armv7a->post_restore_context)
- armv7a->post_restore_context(target);
+ arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
return ERROR_OK;
}
* ap number for every access.
*/
+static int cortex_a8_read_phys_memory(struct target *target,
+ uint32_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer)
+{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
+ int retval = ERROR_INVALID_ARGUMENTS;
+
+ /* cortex_a8 handles unaligned memory access */
+
+// ??? dap_ap_select(swjdp, swjdp_memoryap);
+ LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", address, size, count);
+ if (count && buffer) {
+ switch (size) {
+ case 4:
+ retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
+ break;
+ case 2:
+ retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
+ break;
+ case 1:
+ retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
+ break;
+ }
+ }
+
+ return retval;
+}
+
static int cortex_a8_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
- int retval = ERROR_INVALID_ARGUMENTS;
+ int enabled = 0;
+ uint32_t virt, phys;
/* cortex_a8 handles unaligned memory access */
// ??? dap_ap_select(swjdp, swjdp_memoryap);
+ LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count);
+ cortex_a8_mmu(target, &enabled);
+ if(enabled)
+ {
+ virt = address;
+ cortex_a8_virt2phys(target, virt, &phys);
+ LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", virt, phys);
+ address = phys;
+ }
+
+ return cortex_a8_read_phys_memory(target, address, size, count, buffer);
+}
- if (count && buffer) {
- switch (size) {
- case 4:
- retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
- break;
- case 2:
- retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
- break;
- case 1:
- retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
- break;
- }
- }
-
- return retval;
+static int cortex_a8_write_phys_memory(struct target *target,
+ uint32_t address, uint32_t size,
+ uint32_t count, uint8_t *buffer)
+{
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct adiv5_dap *swjdp = &armv7a->dap;
+ int retval = ERROR_INVALID_ARGUMENTS;
+
+// ??? dap_ap_select(swjdp, swjdp_memoryap);
+
+ LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address, size, count);
+ if (count && buffer) {
+ switch (size) {
+ case 4:
+ retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
+ break;
+ case 2:
+ retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
+ break;
+ case 1:
+ retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
+ break;
+ }
+ }
+
+ /* REVISIT this op is generic ARMv7-A/R stuff */
+ if (retval == ERROR_OK && target->state == TARGET_HALTED)
+ {
+ struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
+
+ retval = dpm->prepare(dpm);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* The Cache handling will NOT work with MMU active, the
+ * wrong addresses will be invalidated!
+ *
+ * For both ICache and DCache, walk all cache lines in the
+ * address range. Cortex-A8 has fixed 64 byte line length.
+ *
+ * REVISIT per ARMv7, these may trigger watchpoints ...
+ */
+
+ /* invalidate I-Cache */
+ if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+ {
+ /* ICIMVAU - Invalidate Cache single entry
+ * with MVA to PoU
+ * MCR p15, 0, r0, c7, c5, 1
+ */
+ for (uint32_t cacheline = address;
+ cacheline < address + size * count;
+ cacheline += 64) {
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
+ cacheline);
+ }
+ }
+
+ /* invalidate D-Cache */
+ if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+ {
+ /* DCIMVAC - Invalidate data Cache line
+ * with MVA to PoC
+ * MCR p15, 0, r0, c7, c6, 1
+ */
+ for (uint32_t cacheline = address;
+ cacheline < address + size * count;
+ cacheline += 64) {
+ retval = dpm->instr_write_data_r0(dpm,
+ ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
+ cacheline);
+ }
+ }
+
+ /* (void) */ dpm->finish(dpm);
+ }
+
+ return retval;
}
static int cortex_a8_write_memory(struct target *target, uint32_t address,
- uint32_t size, uint32_t count, uint8_t *buffer)
+ uint32_t size, uint32_t count, uint8_t *buffer)
{
- struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
- int retval = ERROR_INVALID_ARGUMENTS;
-
-// ??? dap_ap_select(swjdp, swjdp_memoryap);
-
- if (count && buffer) {
- switch (size) {
- case 4:
- retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
- break;
- case 2:
- retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
- break;
- case 1:
- retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
- break;
- }
- }
-
- /* REVISIT this op is generic ARMv7-A/R stuff */
- if (retval == ERROR_OK && target->state == TARGET_HALTED)
- {
- struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
-
- retval = dpm->prepare(dpm);
- if (retval != ERROR_OK)
- return retval;
-
- /* The Cache handling will NOT work with MMU active, the
- * wrong addresses will be invalidated!
- *
- * For both ICache and DCache, walk all cache lines in the
- * address range. Cortex-A8 has fixed 64 byte line length.
- */
-
- /* invalidate I-Cache */
- if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
- {
- /* ICIMVAU - Invalidate Cache single entry
- * with MVA to PoU
- * MCR p15, 0, r0, c7, c5, 1
- */
- for (uint32_t cacheline = address;
- cacheline < address + size * count;
- cacheline += 64) {
- retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
- cacheline);
- }
- }
-
- /* invalidate D-Cache */
- if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
- {
- /* DCIMVAC - Invalidate data Cache line
- * with MVA to PoC
- * MCR p15, 0, r0, c7, c6, 1
- */
- for (uint32_t cacheline = address;
- cacheline < address + size * count;
- cacheline += 64) {
- retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
- cacheline);
- }
- }
-
- /* (void) */ dpm->finish(dpm);
- }
-
- return retval;
+ int enabled = 0;
+ uint32_t virt, phys;
+
+// ??? dap_ap_select(swjdp, swjdp_memoryap);
+
+ LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count);
+ cortex_a8_mmu(target, &enabled);
+ if(enabled)
+ {
+ virt = address;
+ cortex_a8_virt2phys(target, virt, &phys);
+ LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys);
+ address = phys;
+ }
+
+ return cortex_a8_write_phys_memory(target, address, size,
+ count, buffer);
}
static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
}
-static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_a8_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
{
#if 0
u16 dcrdr;
{
struct target *target = priv;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
if (!target_was_examined(target))
return ERROR_OK;
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *swjdp = &armv7a->dap;
int i;
int retval = ERROR_OK;
uint32_t didr, ctypr, ttypr, cpuid;
- LOG_DEBUG("TODO");
+ /* stop assuming this is an OMAP! */
+ LOG_DEBUG("TODO - autoconfigure");
/* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE;
if ((retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
{
- LOG_DEBUG("Examine failed");
+ LOG_DEBUG("Examine %s failed", "CPUID");
return retval;
}
if ((retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
{
- LOG_DEBUG("Examine failed");
+ LOG_DEBUG("Examine %s failed", "CTYPR");
return retval;
}
if ((retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
{
- LOG_DEBUG("Examine failed");
+ LOG_DEBUG("Examine %s failed", "TTYPR");
return retval;
}
if ((retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
{
- LOG_DEBUG("Examine failed");
+ LOG_DEBUG("Examine %s failed", "DIDR");
return retval;
}
cortex_a8->brp_list[i].BRPn = i;
}
- /* Setup Watchpoint Register Pairs */
- cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
- cortex_a8->wrp_num_available = cortex_a8->wrp_num;
- cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp));
- for (i = 0; i < cortex_a8->wrp_num; i++)
- {
- cortex_a8->wrp_list[i].used = 0;
- cortex_a8->wrp_list[i].type = 0;
- cortex_a8->wrp_list[i].value = 0;
- cortex_a8->wrp_list[i].control = 0;
- cortex_a8->wrp_list[i].WRPn = i;
- }
- LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
- cortex_a8->brp_num , cortex_a8->wrp_num);
+ LOG_DEBUG("Configured %i hw breakpoints", cortex_a8->brp_num);
target_set_examined(target);
return ERROR_OK;
{
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
struct arm *armv4_5 = &armv7a->armv4_5_common;
- struct swjdp_common *swjdp = &armv7a->swjdp_info;
+ struct adiv5_dap *dap = &armv7a->dap;
+
+ armv7a->armv4_5_common.dap = dap;
/* Setup struct cortex_a8_common */
cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
cortex_a8->jtag_info.tap = tap;
cortex_a8->jtag_info.scann_size = 4;
- swjdp->dp_select_value = -1;
- swjdp->ap_csw_value = -1;
- swjdp->ap_tar_value = -1;
- swjdp->jtag_info = &cortex_a8->jtag_info;
- swjdp->memaccess_tck = 80;
+ /* Leave (only) generic DAP stuff for debugport_init() */
+ dap->jtag_info = &cortex_a8->jtag_info;
+ dap->memaccess_tck = 80;
/* Number of bits for tar autoincrement, impl. dep. at least 10 */
- swjdp->tar_autoincr_block = (1 << 10);
+ dap->tar_autoincr_block = (1 << 10);
cortex_a8->fast_reg_read = 0;
+ /* Set default value */
+ cortex_a8->current_address_mode = ARM_MODE_ANY;
+
/* register arch-specific functions */
armv7a->examine_debug_reason = NULL;
armv7a->post_debug_entry = cortex_a8_post_debug_entry;
armv7a->pre_restore_context = NULL;
- armv7a->post_restore_context = NULL;
armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
-// armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
- armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
- armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
-// armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
-// armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
+ armv7a->armv4_5_mmu.get_ttb = cortex_a8_get_ttb;
+ armv7a->armv4_5_mmu.read_memory = cortex_a8_read_phys_memory;
+ armv7a->armv4_5_mmu.write_memory = cortex_a8_write_phys_memory;
+ armv7a->armv4_5_mmu.disable_mmu_caches = cortex_a8_disable_mmu_caches;
+ armv7a->armv4_5_mmu.enable_mmu_caches = cortex_a8_enable_mmu_caches;
armv7a->armv4_5_mmu.has_tiny_pages = 1;
armv7a->armv4_5_mmu.mmu_enabled = 0;
// arm7_9->handle_target_request = cortex_a8_handle_target_request;
/* REVISIT v7a setup should be in a v7a-specific routine */
- armv4_5_init_arch_info(target, armv4_5);
+ arm_init_arch_info(target, armv4_5);
armv7a->common_magic = ARMV7_COMMON_MAGIC;
target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
return ERROR_OK;
}
+static uint32_t cortex_a8_get_ttb(struct target *target)
+{
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ uint32_t ttb = 0, retval = ERROR_OK;
+
+ /* current_address_mode is set inside cortex_a8_virt2phys()
+ where we can determine if address belongs to user or kernel */
+ if(cortex_a8->current_address_mode == ARM_MODE_SVC)
+ {
+ /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
+ retval = armv7a->armv4_5_common.mrc(target, 15,
+ 0, 1, /* op1, op2 */
+ 2, 0, /* CRn, CRm */
+ &ttb);
+ }
+ else if(cortex_a8->current_address_mode == ARM_MODE_USR)
+ {
+ /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
+ retval = armv7a->armv4_5_common.mrc(target, 15,
+ 0, 0, /* op1, op2 */
+ 2, 0, /* CRn, CRm */
+ &ttb);
+ }
+ /* we don't know whose address is: user or kernel
+ we assume that if we are in kernel mode then
+ address belongs to kernel else if in user mode
+ - to user */
+ else if(armv7a->armv4_5_common.core_mode == ARM_MODE_SVC)
+ {
+ /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
+ retval = armv7a->armv4_5_common.mrc(target, 15,
+ 0, 1, /* op1, op2 */
+ 2, 0, /* CRn, CRm */
+ &ttb);
+ }
+ else if(armv7a->armv4_5_common.core_mode == ARM_MODE_USR)
+ {
+ /* MRC p15,0,<Rt>,c1,c0,0 ; Read CP15 System Control Register */
+ retval = armv7a->armv4_5_common.mrc(target, 15,
+ 0, 0, /* op1, op2 */
+ 2, 0, /* CRn, CRm */
+ &ttb);
+ }
+ /* finaly we don't know whose ttb to use: user or kernel */
+ else
+ LOG_ERROR("Don't know how to get ttb for current mode!!!");
+
+ ttb &= 0xffffc000;
+
+ return ttb;
+}
+
+static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
+ int d_u_cache, int i_cache)
+{
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ uint32_t cp15_control;
+
+ /* read cp15 control register */
+ armv7a->armv4_5_common.mrc(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ &cp15_control);
+
+
+ if (mmu)
+ cp15_control &= ~0x1U;
+
+ if (d_u_cache)
+ cp15_control &= ~0x4U;
+
+ if (i_cache)
+ cp15_control &= ~0x1000U;
+
+ armv7a->armv4_5_common.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cp15_control);
+}
+
+static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
+ int d_u_cache, int i_cache)
+{
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ uint32_t cp15_control;
+
+ /* read cp15 control register */
+ armv7a->armv4_5_common.mrc(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ &cp15_control);
+
+ if (mmu)
+ cp15_control |= 0x1U;
+
+ if (d_u_cache)
+ cp15_control |= 0x4U;
+
+ if (i_cache)
+ cp15_control |= 0x1000U;
+
+ armv7a->armv4_5_common.mcr(target, 15,
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ cp15_control);
+}
+
+
+static int cortex_a8_mmu(struct target *target, int *enabled)
+{
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("%s: target not halted", __func__);
+ return ERROR_TARGET_INVALID;
+ }
+
+ *enabled = target_to_cortex_a8(target)->armv7a_common.armv4_5_mmu.mmu_enabled;
+ return ERROR_OK;
+}
+
+static int cortex_a8_virt2phys(struct target *target,
+ uint32_t virt, uint32_t *phys)
+{
+ uint32_t cb;
+ int domain;
+ uint32_t ap;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ // struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+
+ /* We assume that virtual address is separated
+ between user and kernel in Linux style:
+ 0x00000000-0xbfffffff - User space
+ 0xc0000000-0xffffffff - Kernel space */
+ if( virt < 0xc0000000 ) /* Linux user space */
+ cortex_a8->current_address_mode = ARM_MODE_USR;
+ else /* Linux kernel */
+ cortex_a8->current_address_mode = ARM_MODE_SVC;
+ uint32_t ret;
+ int retval = armv4_5_mmu_translate_va(target,
+ &armv7a->armv4_5_mmu, virt, &cb, &domain, &ap, &ret);
+ if (retval != ERROR_OK)
+ return retval;
+ /* Reset the flag. We don't want someone else to use it by error */
+ cortex_a8->current_address_mode = ARM_MODE_ANY;
+
+ *phys = ret;
+ return ERROR_OK;
+}
+
COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
{
struct target *target = get_current_target(CMD_CTX);
static const struct command_registration cortex_a8_exec_command_handlers[] = {
{
.name = "cache_info",
- .handler = &cortex_a8_handle_cache_info_command,
+ .handler = cortex_a8_handle_cache_info_command,
.mode = COMMAND_EXEC,
.help = "display information about target caches",
},
{
.name = "dbginit",
- .handler = &cortex_a8_handle_dbginit_command,
+ .handler = cortex_a8_handle_dbginit_command,
.mode = COMMAND_EXEC,
.help = "Initialize core debug",
},
.deassert_reset = cortex_a8_deassert_reset,
.soft_reset_halt = NULL,
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+ /* REVISIT allow exporting VFP3 registers ... */
+ .get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = cortex_a8_read_memory,
.write_memory = cortex_a8_write_memory,
.target_create = cortex_a8_target_create,
.init_target = cortex_a8_init_target,
.examine = cortex_a8_examine,
+
+ .read_phys_memory = cortex_a8_read_phys_memory,
+ .write_phys_memory = cortex_a8_write_phys_memory,
+ .mmu = cortex_a8_mmu,
+ .virt2phys = cortex_a8_virt2phys,
+
};
projects / fw / openocd / blobdiff