mips: fix gaffe when removing dynamic array allocation

[fw/openocd] / src / target / cortex_a8.c

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 71de3b799267e251a92711ea7482d63b02cea1a6..b006e81a64df7f91547fce2a4020b70d2042c083 100644 (file)
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -457,7 +457,7 @@ static int cortex_a8_resume(struct target *target, int current,
                uint32_t address, int handle_breakpoints, int debug_execution)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+       struct arm *armv4_5 = &armv7a->armv4_5_common;
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
 
 //     struct breakpoint *breakpoint = NULL;
@@ -496,8 +496,7 @@ static int cortex_a8_resume(struct target *target, int current,
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
        resume_pc = buf_get_u32(
-                       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, 15).value,
+                       armv4_5->core_cache->reg_list[15].value,
                        0, 32);
        if (!current)
                resume_pc = address;
@@ -522,13 +521,10 @@ static int cortex_a8_resume(struct target *target, int current,
                return ERROR_FAIL;
        }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
-       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, 15).value,
+       buf_set_u32(armv4_5->core_cache->reg_list[15].value,
                        0, 32, resume_pc);
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                       armv4_5->core_mode, 15).dirty = 1;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                       armv4_5->core_mode, 15).valid = 1;
+       armv4_5->core_cache->reg_list[15].dirty = 1;
+       armv4_5->core_cache->reg_list[15].valid = 1;
 
        cortex_a8_restore_context(target);
 
@@ -587,7 +583,7 @@ static int cortex_a8_debug_entry(struct target *target)
        struct working_area *regfile_working_area = NULL;
        struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+       struct arm *armv4_5 = &armv7a->armv4_5_common;
        struct swjdp_common *swjdp = &armv7a->swjdp_info;
        struct reg *reg;
 
@@ -650,34 +646,10 @@ static int cortex_a8_debug_entry(struct target *target)
 
        arm_set_cpsr(armv4_5, cpsr);
 
-       i = (cpsr >> 5) & 1;    /* T */
-       i |= (cpsr >> 23) & 1;  /* J << 1 */
-       switch (i) {
-       case 0: /* J = 0, T = 0 */
-               armv4_5->core_state = ARMV4_5_STATE_ARM;
-               break;
-       case 1: /* J = 0, T = 1 */
-               armv4_5->core_state = ARMV4_5_STATE_THUMB;
-               break;
-       case 2: /* J = 1, T = 0 */
-               LOG_WARNING("Jazelle state -- not handled");
-               armv4_5->core_state = ARMV4_5_STATE_JAZELLE;
-               break;
-       case 3: /* J = 1, T = 1 */
-               /* ThumbEE is very much like Thumb, but some of the
-                * instructions are different.  Single stepping and
-                * breakpoints need updating...
-                */
-               LOG_WARNING("ThumbEE -- incomplete support");
-               armv4_5->core_state = ARM_STATE_THUMB_EE;
-               break;
-       }
-
        /* update cache */
        for (i = 0; i <= ARM_PC; i++)
        {
-               reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                                       armv4_5->core_mode, i);
+               reg = arm_reg_current(armv4_5, i);
 
                buf_set_u32(reg->value, 0, 32, regfile[i]);
                reg->valid = 1;
@@ -695,13 +667,10 @@ static int cortex_a8_debug_entry(struct target *target)
                // ARM state
                regfile[ARM_PC] -= 8;
        }
-       buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, ARM_PC).value,
-                       0, 32, regfile[ARM_PC]);
 
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
-               .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-                               armv4_5->core_mode, 0).valid;
+       reg = armv4_5->core_cache->reg_list + 15;
+       buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]);
+       reg->dirty = reg->valid;
        ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
                .dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
                                armv4_5->core_mode, 15).valid;
@@ -766,7 +735,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
                int handle_breakpoints)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
-       struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+       struct arm *armv4_5 = &armv7a->armv4_5_common;
        struct breakpoint *breakpoint = NULL;
        struct breakpoint stepbreakpoint;
 
@@ -938,7 +907,7 @@ static int cortex_a8_load_core_reg_u32(struct target *target, int num,
                armv4_5_mode_t mode, uint32_t * value)
 {
        int retval;
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
 
        if ((num <= ARM_CPSR))
        {
@@ -976,7 +945,7 @@ static int cortex_a8_store_core_reg_u32(struct target *target, int num,
 {
        int retval;
 //     uint32_t reg;
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
 
 #ifdef ARMV7_GDB_HACKS
        /* If the LR register is being modified, make sure it will put us
@@ -1021,7 +990,7 @@ static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
 {
        uint32_t value;
        int retval;
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
        struct reg *cpsr_r = NULL;
        uint32_t cpsr = 0;
        unsigned cookie = num;
@@ -1076,7 +1045,7 @@ static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
                int num, enum armv4_5_mode mode, uint32_t value)
 {
        int retval;
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
        struct reg *cpsr_r = NULL;
        uint32_t cpsr = 0;
        unsigned cookie = num;
@@ -1607,7 +1576,7 @@ static int cortex_a8_examine(struct target *target)
 static void cortex_a8_build_reg_cache(struct target *target)
 {
        struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-       struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+       struct arm *armv4_5 = target_to_armv4_5(target);
 
        armv4_5->core_type = ARM_MODE_MON;