* Copyright (C) 2009 by Dirk Behme *
* dirk.behme@gmail.com - copy from cortex_m3 *
* *
+ * Copyright (C) 2010 Øyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#include "target_request.h"
#include "target_type.h"
#include "arm_opcodes.h"
+#include <helper/time_support.h>
static int cortex_a8_poll(struct target *target);
static int cortex_a8_debug_entry(struct target *target);
static int cortex_a8_mmu(struct target *target, int *enabled);
static int cortex_a8_virt2phys(struct target *target,
uint32_t virt, uint32_t *phys);
-static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache);
-static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache);
-static uint32_t cortex_a8_get_ttb(struct target *target);
+static int cortex_a8_get_ttb(struct target *target, uint32_t *result);
/*
/* The debugport might be uninitialised so try twice */
retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval != ERROR_OK)
- mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+ {
+ /* try again */
+ retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+ if (retval == ERROR_OK)
+ {
+ LOG_USER("Locking debug access failed on first, but succeeded on second try.");
+ }
+ }
+ if (retval != ERROR_OK)
+ return retval;
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
+ if (retval != ERROR_OK)
+ return retval;
+
/* Enabling of instruction execution in debug mode is done in debug_entry code */
/* Resync breakpoint registers */
- /* Since this is likley called from init or reset, update targtet state information*/
- cortex_a8_poll(target);
+ /* Since this is likely called from init or reset, update target state information*/
+ retval = cortex_a8_poll(target);
return retval;
}
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
/* Wait for InstrCompl bit to be set */
+ long long then = timeval_ms();
while ((dscr & DSCR_INSTR_COMP) == 0)
{
retval = mem_ap_read_atomic_u32(swjdp,
LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
return retval;
}
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ return ERROR_FAIL;
+ }
}
- mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
+ retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
+ if (retval != ERROR_OK)
+ return retval;
+ then = timeval_ms();
do
{
retval = mem_ap_read_atomic_u32(swjdp,
LOG_ERROR("Could not read DSCR register");
return retval;
}
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ return ERROR_FAIL;
+ }
}
while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = &armv7a->dap;
- cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
- cortex_a8_dap_write_coreregister_u32(target, address, 0);
- cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
+ retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_dap_write_coreregister_u32(target, address, 0);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0), NULL);
+ if (retval != ERROR_OK)
+ return retval;
+
dap_ap_select(swjdp, swjdp_memoryap);
- mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address);
+ retval = mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address);
+ if (retval != ERROR_OK)
+ return retval;
dap_ap_select(swjdp, swjdp_debugap);
return retval;
if (reg < 15)
{
/* Rn to DCCTX, "MCR p14, 0, Rn, c0, c5, 0" 0xEE00nE15 */
- cortex_a8_exec_opcode(target,
+ retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(14, 0, reg, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
else if (reg == 15)
{
/* "MOV r0, r15"; then move r0 to DCCTX */
- cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
- cortex_a8_exec_opcode(target,
+ retval = cortex_a8_exec_opcode(target, 0xE1A0000F, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
else
{
/* "MRS r0, CPSR" or "MRS r0, SPSR"
* then move r0 to DCCTX
*/
- cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
- cortex_a8_exec_opcode(target,
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, reg & 1), &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
/* Wait for DTRRXfull then read DTRRTX */
+ long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0)
{
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for cortex_a8_exec_opcode");
+ return ERROR_FAIL;
+ }
}
retval = mem_ap_read_atomic_u32(swjdp,
/* Check that DCCRX is not full */
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
if (dscr & DSCR_DTR_RX_FULL)
{
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
if (Rd > 17)
LOG_DEBUG("write DCC 0x%08" PRIx32, value);
retval = mem_ap_write_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRRX, value);
+ if (retval != ERROR_OK)
+ return retval;
if (Rd < 15)
{
/* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
else if (Rd == 15)
{
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
* then "mov r15, r0"
*/
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
- cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_exec_opcode(target, 0xE1A0F000, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
else
{
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15
* then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
*/
- cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
- cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, Rd & 1),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
/* "Prefetch flush" after modifying execution status in CPSR */
if (Rd == 16)
- cortex_a8_exec_opcode(target,
+ {
+ retval = cortex_a8_exec_opcode(target,
ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
}
return retval;
dscr = *dscr_p;
/* Wait for DTRRXfull */
+ long long then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for read dcc");
+ return ERROR_FAIL;
+ }
}
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+ if (retval != ERROR_OK)
+ return retval;
//LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
if (dscr_p)
int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */
- do {
+ long long then = timeval_ms();
+ for (;;)
+ {
retval = mem_ap_read_atomic_u32(swjdp,
a8->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
- } while ((dscr & DSCR_INSTR_COMP) == 0);
+ if (retval != ERROR_OK)
+ return retval;
+ if ((dscr & DSCR_INSTR_COMP) != 0)
+ break;
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for dpm prepare");
+ return ERROR_FAIL;
+ }
+ }
/* this "should never happen" ... */
if (dscr & DSCR_DTR_RX_FULL) {
a8->armv7a_common.armv4_5_common.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
}
return retval;
uint32_t dscr = DSCR_INSTR_COMP;
retval = cortex_a8_write_dcc(a8, data);
+ if (retval != ERROR_OK)
+ return retval;
return cortex_a8_exec_opcode(
a8->armv7a_common.armv4_5_common.target,
int retval;
retval = cortex_a8_write_dcc(a8, data);
+ if (retval != ERROR_OK)
+ return retval;
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
retval = cortex_a8_exec_opcode(
a8->armv7a_common.armv4_5_common.target,
ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
/* then the opcode, taking data from R0 */
retval = cortex_a8_exec_opcode(
a8->armv7a_common.armv4_5_common.target,
opcode,
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
return cortex_a8_read_dcc(a8, data, &dscr);
}
a8->armv7a_common.armv4_5_common.target,
opcode,
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
/* write R0 to DCC */
retval = cortex_a8_exec_opcode(
a8->armv7a_common.armv4_5_common.target,
ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
&dscr);
+ if (retval != ERROR_OK)
+ return retval;
return cortex_a8_read_dcc(a8, data, &dscr);
}
*/
retval = mem_ap_write_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DRCR, 0x1);
+ if (retval != ERROR_OK)
+ goto out;
/*
* enter halting debug mode
*/
- mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ goto out;
+
retval = mem_ap_write_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
-
if (retval != ERROR_OK)
goto out;
- do {
- mem_ap_read_atomic_u32(swjdp,
+ long long then = timeval_ms();
+ for (;;)
+ {
+ retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- } while ((dscr & DSCR_CORE_HALTED) == 0);
+ if (retval != ERROR_OK)
+ goto out;
+ if ((dscr & DSCR_CORE_HALTED) != 0)
+ {
+ break;
+ }
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for halt");
+ return ERROR_FAIL;
+ }
+ }
target->debug_reason = DBG_REASON_DBGRQ;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *armv4_5 = &armv7a->armv4_5_common;
struct adiv5_dap *swjdp = &armv7a->dap;
+ int retval;
// struct breakpoint *breakpoint = NULL;
uint32_t resume_pc, dscr;
armv4_5->pc->dirty = 1;
armv4_5->pc->valid = 1;
- cortex_a8_restore_context(target, handle_breakpoints);
+ retval = cortex_a8_restore_context(target, handle_breakpoints);
+ if (retval != ERROR_OK)
+ return retval;
#if 0
/* the front-end may request us not to handle breakpoints */
* REVISIT: for single stepping, we probably want to
* disable IRQs by default, with optional override...
*/
- mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
+ retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
+ if (retval != ERROR_OK)
+ return retval;
- do {
- mem_ap_read_atomic_u32(swjdp,
+ long long then = timeval_ms();
+ for (;;)
+ {
+ retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
- } while ((dscr & DSCR_CORE_RESTARTED) == 0);
+ if (retval != ERROR_OK)
+ return retval;
+ if ((dscr & DSCR_CORE_RESTARTED) != 0)
+ break;
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for resume");
+ return ERROR_FAIL;
+ }
+ }
target->debug_reason = DBG_REASON_NOTHALTED;
target->state = TARGET_RUNNING;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
/* REVISIT surely we should not re-read DSCR !! */
- mem_ap_read_atomic_u32(swjdp,
+ retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
/* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
* imprecise data aborts get discarded by issuing a Data
dscr |= DSCR_ITR_EN;
retval = mem_ap_write_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, dscr);
+ if (retval != ERROR_OK)
+ return retval;
/* Examine debug reason */
arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_WFAR,
&wfar);
+ if (retval != ERROR_OK)
+ return retval;
arm_dpm_report_wfar(&armv7a->dpm, wfar);
}
else
{
dap_ap_select(swjdp, swjdp_memoryap);
- cortex_a8_read_regs_through_mem(target,
+ retval = cortex_a8_read_regs_through_mem(target,
regfile_working_area->address, regfile);
dap_ap_select(swjdp, swjdp_memoryap);
target_free_working_area(target, regfile_working_area);
+ if (retval != ERROR_OK)
+ {
+ return retval;
+ }
/* read Current PSR */
- cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+ if (retval != ERROR_OK)
+ return retval;
dap_ap_select(swjdp, swjdp_debugap);
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
/* Are we in an exception handler */
// armv4_5->exception_number = 0;
if (armv7a->post_debug_entry)
- armv7a->post_debug_entry(target);
+ {
+ retval = armv7a->post_debug_entry(target);
+ if (retval != ERROR_OK)
+ return retval;
+ }
return retval;
}
-static void cortex_a8_post_debug_entry(struct target *target)
+static int cortex_a8_post_debug_entry(struct target *target)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
&cortex_a8->cp15_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
0, 1, /* op1, op2 */
0, 0, /* CRn, CRm */
&cache_type_reg);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("cp15 cache type: %8.8x", (unsigned) cache_type_reg);
/* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
(cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
-
+ return ERROR_OK;
}
static int cortex_a8_step(struct target *target, int current, uint32_t address,
struct breakpoint *breakpoint = NULL;
struct breakpoint stepbreakpoint;
struct reg *r;
-
- int timeout = 100;
+ int retval;
if (target->state != TARGET_HALTED)
{
target->debug_reason = DBG_REASON_SINGLESTEP;
- cortex_a8_resume(target, 1, address, 0, 0);
+ retval = cortex_a8_resume(target, 1, address, 0, 0);
+ if (retval != ERROR_OK)
+ return retval;
+ long long then = timeval_ms();
while (target->state != TARGET_HALTED)
{
- cortex_a8_poll(target);
- if (--timeout == 0)
+ retval = cortex_a8_poll(target);
+ if (retval != ERROR_OK)
+ return retval;
+ if (timeval_ms() > then + 1000)
{
- LOG_WARNING("timeout waiting for target halt");
- break;
+ LOG_ERROR("timeout waiting for target halt");
+ return ERROR_FAIL;
}
}
cortex_a8_unset_breakpoint(target, &stepbreakpoint);
- if (timeout > 0)
- target->debug_reason = DBG_REASON_BREAKPOINT;
+
+ target->debug_reason = DBG_REASON_BREAKPOINT;
if (breakpoint)
cortex_a8_set_breakpoint(target, breakpoint, 0);
if (armv7a->pre_restore_context)
armv7a->pre_restore_context(target);
- arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
-
- return ERROR_OK;
+ return arm_dpm_write_dirty_registers(&armv7a->dpm, bpwp);
}
/*
- * Cortex-A8 Breakpoint and watchpoint fuctions
+ * Cortex-A8 Breakpoint and watchpoint functions
*/
/* Setup hardware Breakpoint Register Pair */
brp_list[brp_i].used = 1;
brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
brp_list[brp_i].control = control;
- cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
- cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
brp_list[brp_i].control,
brp_list[brp_i].value);
brp_list[brp_i].used = 0;
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
- cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
- cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
+ if (retval != ERROR_OK)
+ return retval;
}
else
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
#if 0
-/* It is perfectly possible to remove brakpoints while the taget is running */
+/* It is perfectly possible to remove breakpoints while the target is running */
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
/*
- * Cortex-A8 Reset fuctions
+ * Cortex-A8 Reset functions
*/
static int cortex_a8_assert_reset(struct target *target)
jtag_add_reset(0, 0);
retval = cortex_a8_poll(target);
+ if (retval != ERROR_OK)
+ return retval;
if (target->reset_halt) {
if (target->state != TARGET_HALTED) {
{
int enabled = 0;
uint32_t virt, phys;
+ int retval;
/* cortex_a8 handles unaligned memory access */
// ??? dap_ap_select(swjdp, swjdp_memoryap);
LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, size, count);
- cortex_a8_mmu(target, &enabled);
+ retval = cortex_a8_mmu(target, &enabled);
+ if (retval != ERROR_OK)
+ return retval;
+
if(enabled)
{
virt = address;
- cortex_a8_virt2phys(target, virt, &phys);
+ retval = cortex_a8_virt2phys(target, virt, &phys);
+ if (retval != ERROR_OK)
+ return retval;
+
LOG_DEBUG("Reading at virtual address. Translating v:0x%x to r:0x%x", virt, phys);
address = phys;
}
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
cacheline);
+ if (retval != ERROR_OK)
+ return retval;
}
}
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
cacheline);
+ if (retval != ERROR_OK)
+ return retval;
}
}
{
int enabled = 0;
uint32_t virt, phys;
+ int retval;
// ??? dap_ap_select(swjdp, swjdp_memoryap);
LOG_DEBUG("Writing memory to address 0x%x; size %d; count %d", address, size, count);
- cortex_a8_mmu(target, &enabled);
+ retval = cortex_a8_mmu(target, &enabled);
+ if (retval != ERROR_OK)
+ return retval;
if(enabled)
{
virt = address;
- cortex_a8_virt2phys(target, virt, &phys);
+ retval = cortex_a8_virt2phys(target, virt, &phys);
+ if (retval != ERROR_OK)
+ return retval;
LOG_DEBUG("Writing to virtual address. Translating v:0x%x to r:0x%x", virt, phys);
address = phys;
}
struct target *target = priv;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = &armv7a->dap;
+ int retval;
if (!target_was_examined(target))
return ERROR_OK;
uint8_t data = 0;
uint8_t ctrl = 0;
- cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ retval = cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
/* check if we have data */
if (ctrl & (1 << 0))
/* we assume target is quick enough */
request = data;
- cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ retval = cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
request |= (data << 8);
- cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ retval = cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
request |= (data << 16);
- cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ retval = cortex_a8_dcc_read(swjdp, &data, &ctrl);
+ if (retval != ERROR_OK)
+ return retval;
request |= (data << 24);
target_request(target, request);
}
/* We do one extra read to ensure DAP is configured,
* we call ahbap_debugport_init(swjdp) instead
*/
- ahbap_debugport_init(swjdp);
- mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
+ retval = ahbap_debugport_init(swjdp);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
+ if (retval != ERROR_OK)
+ return retval;
+
if ((retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
{
LOG_DEBUG("didr = 0x%08" PRIx32, didr);
armv7a->armv4_5_common.core_type = ARM_MODE_MON;
- cortex_a8_dpm_setup(cortex_a8, didr);
+ retval = cortex_a8_dpm_setup(cortex_a8, didr);
+ if (retval != ERROR_OK)
+ return retval;
/* Setup Breakpoint Register Pairs */
cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
{
struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
- cortex_a8_init_arch_info(target, cortex_a8, target->tap);
-
- return ERROR_OK;
+ return cortex_a8_init_arch_info(target, cortex_a8, target->tap);
}
-static uint32_t cortex_a8_get_ttb(struct target *target)
+static int cortex_a8_get_ttb(struct target *target, uint32_t *result)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
0, 1, /* op1, op2 */
2, 0, /* CRn, CRm */
&ttb);
+ if (retval != ERROR_OK)
+ return retval;
}
else if(cortex_a8->current_address_mode == ARM_MODE_USR)
{
0, 0, /* op1, op2 */
2, 0, /* CRn, CRm */
&ttb);
+ if (retval != ERROR_OK)
+ return retval;
}
/* we don't know whose address is: user or kernel
we assume that if we are in kernel mode then
0, 1, /* op1, op2 */
2, 0, /* CRn, CRm */
&ttb);
+ if (retval != ERROR_OK)
+ return retval;
}
else if(armv7a->armv4_5_common.core_mode == ARM_MODE_USR)
{
0, 0, /* op1, op2 */
2, 0, /* CRn, CRm */
&ttb);
+ if (retval != ERROR_OK)
+ return retval;
}
- /* finaly we don't know whose ttb to use: user or kernel */
+ /* finally we don't know whose ttb to use: user or kernel */
else
LOG_ERROR("Don't know how to get ttb for current mode!!!");
ttb &= 0xffffc000;
- return ttb;
+ *result = ttb;
+
+ return ERROR_OK;
}
-static void cortex_a8_disable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_disable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- armv7a->armv4_5_common.mrc(target, 15,
+ retval = armv7a->armv4_5_common.mrc(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
&cp15_control);
+ if (retval != ERROR_OK)
+ return retval;
if (mmu)
if (i_cache)
cp15_control &= ~0x1000U;
- armv7a->armv4_5_common.mcr(target, 15,
+ retval = armv7a->armv4_5_common.mcr(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
cp15_control);
+ return retval;
}
-static void cortex_a8_enable_mmu_caches(struct target *target, int mmu,
+static int cortex_a8_enable_mmu_caches(struct target *target, int mmu,
int d_u_cache, int i_cache)
{
struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
uint32_t cp15_control;
+ int retval;
/* read cp15 control register */
- armv7a->armv4_5_common.mrc(target, 15,
+ retval = armv7a->armv4_5_common.mrc(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
&cp15_control);
+ if (retval != ERROR_OK)
+ return retval;
if (mmu)
cp15_control |= 0x1U;
if (i_cache)
cp15_control |= 0x1000U;
- armv7a->armv4_5_common.mcr(target, 15,
+ retval = armv7a->armv4_5_common.mcr(target, 15,
0, 0, /* op1, op2 */
1, 0, /* CRn, CRm */
cp15_control);
+ return retval;
}
projects / fw / openocd / blobdiff