#include "target_request.h"
#include "target_type.h"
-/* cli handling */
-int cortex_a8_register_commands(struct command_context_s *cmd_ctx);
-
-/* forward declarations */
-int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp);
-int cortex_a8_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target);
-int cortex_a8_examine(struct target_s *target);
-int cortex_a8_poll(target_t *target);
-int cortex_a8_halt(target_t *target);
-int cortex_a8_resume(struct target_s *target, int current, uint32_t address,
- int handle_breakpoints, int debug_execution);
-int cortex_a8_step(struct target_s *target, int current, uint32_t address,
- int handle_breakpoints);
-int cortex_a8_debug_entry(target_t *target);
-int cortex_a8_restore_context(target_t *target);
-int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
- uint32_t count, uint8_t *buffer);
-int cortex_a8_set_breakpoint(struct target_s *target,
- breakpoint_t *breakpoint, uint8_t matchmode);
-int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_poll(struct target *target);
+static int cortex_a8_debug_entry(struct target *target);
+static int cortex_a8_restore_context(struct target *target);
+static int cortex_a8_set_breakpoint(struct target *target,
+ struct breakpoint *breakpoint, uint8_t matchmode);
+static int cortex_a8_unset_breakpoint(struct target *target,
+ struct breakpoint *breakpoint);
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum);
-int cortex_a8_dap_write_coreregister_u32(target_t *target,
+static int cortex_a8_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum);
-int cortex_a8_assert_reset(target_t *target);
-int cortex_a8_deassert_reset(target_t *target);
-
-target_type_t cortexa8_target =
-{
- .name = "cortex_a8",
-
- .poll = cortex_a8_poll,
- .arch_state = armv7a_arch_state,
-
- .target_request_data = NULL,
-
- .halt = cortex_a8_halt,
- .resume = cortex_a8_resume,
- .step = cortex_a8_step,
-
- .assert_reset = cortex_a8_assert_reset,
- .deassert_reset = cortex_a8_deassert_reset,
- .soft_reset_halt = NULL,
-
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
- .read_memory = cortex_a8_read_memory,
- .write_memory = cortex_a8_write_memory,
- .bulk_write_memory = cortex_a8_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
-
- .run_algorithm = armv4_5_run_algorithm,
-
- .add_breakpoint = cortex_a8_add_breakpoint,
- .remove_breakpoint = cortex_a8_remove_breakpoint,
- .add_watchpoint = NULL,
- .remove_watchpoint = NULL,
-
- .register_commands = cortex_a8_register_commands,
- .target_create = cortex_a8_target_create,
- .init_target = cortex_a8_init_target,
- .examine = cortex_a8_examine,
- .quit = NULL
-};
-
/*
* FIXME do topology discovery using the ROM; don't
* assume this is an OMAP3.
/*
* Cortex-A8 Basic debug access, very low level assumes state is saved
*/
-int cortex_a8_init_debug_access(target_t *target)
+static int cortex_a8_init_debug_access(struct target *target)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
int retval;
uint32_t dummy;
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
- /* Enabling of instruction execution in debug mode is done in debug_entry code */
-
+ /* Enabling of instruction execution in debug mode is done in debug_entry code */
+
/* Resync breakpoint registers */
-
+
/* Since this is likley called from init or reset, update targtet state information*/
cortex_a8_poll(target);
-
+
return retval;
}
-int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
+int cortex_a8_exec_opcode(struct target *target, uint32_t opcode)
{
uint32_t dscr;
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
do
Read core register with very few exec_opcode, fast but needs work_area.
This can cause problems with MMU active.
**************************************************************************/
-int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
+static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t address,
uint32_t * regfile)
{
int retval = ERROR_OK;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
cortex_a8_dap_write_coreregister_u32(target, address, 0);
return retval;
}
-int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
+static int cortex_a8_read_cp(struct target *target, uint32_t *value, uint8_t CP,
uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
{
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2));
/* Move R0 to DTRTX */
return retval;
}
-int cortex_a8_write_cp(target_t *target, uint32_t value,
+static int cortex_a8_write_cp(struct target *target, uint32_t value,
uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
{
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ uint32_t dscr;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
+
+ LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
+
+ /* Check that DCCRX is not full */
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (dscr & (1 << DSCR_DTR_RX_FULL))
+ {
+ LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+ /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+ }
retval = mem_ap_write_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRRX, value);
return retval;
}
-int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_read_cp15(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t *value)
{
return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
}
-int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
+static int cortex_a8_write_cp15(struct target *target, uint32_t op1, uint32_t op2,
uint32_t CRn, uint32_t CRm, uint32_t value)
{
return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
}
-int cortex_a8_dap_read_coreregister_u32(target_t *target,
+static int cortex_a8_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+ return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
+}
+
+static int cortex_a8_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+ return cortex_a8_write_cp15(target, op1, op2, CRn, CRm, value);
+}
+
+
+
+static int cortex_a8_dap_read_coreregister_u32(struct target *target,
uint32_t *value, int regnum)
{
int retval = ERROR_OK;
uint8_t reg = regnum&0xFF;
uint32_t dscr;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
if (reg > 16)
return retval;
return retval;
}
-int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum)
+static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint32_t value, int regnum)
{
int retval = ERROR_OK;
uint8_t Rd = regnum&0xFF;
+ uint32_t dscr;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
+
+ LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
+
+ /* Check that DCCRX is not full */
+ retval = mem_ap_read_atomic_u32(swjdp,
+ armv7a->debug_base + CPUDBG_DSCR, &dscr);
+ if (dscr & (1 << DSCR_DTR_RX_FULL))
+ {
+ LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+ /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
+ cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+ }
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
if (Rd > 16)
return retval;
}
/* Write to memory mapped registers directly with no cache or mmu handling */
-int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value)
+static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_t address, uint32_t value)
{
int retval;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
retval = mem_ap_write_atomic_u32(swjdp, address, value);
* Cortex-A8 Run control
*/
-int cortex_a8_poll(target_t *target)
+static int cortex_a8_poll(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
-
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
enum target_state prev_target_state = target->state;
-
uint8_t saved_apsel = dap_ap_get_select(swjdp);
+
dap_ap_select(swjdp, swjdp_debugap);
retval = mem_ap_read_atomic_u32(swjdp,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
return retval;
}
-int cortex_a8_halt(target_t *target)
+static int cortex_a8_halt(struct target *target)
{
int retval = ERROR_OK;
uint32_t dscr;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
dap_ap_select(swjdp, swjdp_debugap);
return retval;
}
-int cortex_a8_resume(struct target_s *target, int current,
+static int cortex_a8_resume(struct target *target, int current,
uint32_t address, int handle_breakpoints, int debug_execution)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
-// breakpoint_t *breakpoint = NULL;
+// struct breakpoint *breakpoint = NULL;
uint32_t resume_pc, dscr;
uint8_t saved_apsel = dap_ap_get_select(swjdp);
return ERROR_OK;
}
-int cortex_a8_debug_entry(target_t *target)
+static int cortex_a8_debug_entry(struct target *target)
{
int i;
uint32_t regfile[16], pc, cpsr, dscr;
int retval = ERROR_OK;
- working_area_t *regfile_working_area = NULL;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
- if (armv7a->pre_debug_entry)
- armv7a->pre_debug_entry(target);
+ struct working_area *regfile_working_area = NULL;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
}
-void cortex_a8_post_debug_entry(target_t *target)
+static void cortex_a8_post_debug_entry(struct target *target)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
// cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
/* examine cp15 control reg */
}
-int cortex_a8_step(struct target_s *target, int current, uint32_t address,
+static int cortex_a8_step(struct target *target, int current, uint32_t address,
int handle_breakpoints)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- breakpoint_t *breakpoint = NULL;
- breakpoint_t stepbreakpoint;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
+ struct breakpoint *breakpoint = NULL;
+ struct breakpoint stepbreakpoint;
int timeout = 100;
return ERROR_OK;
}
-int cortex_a8_restore_context(target_t *target)
+static int cortex_a8_restore_context(struct target *target)
{
int i;
uint32_t value;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct armv4_5_common_s *armv4_5 = &armv7a->armv4_5_common;
LOG_DEBUG(" ");
}
+#if 0
/*
* Cortex-A8 Core register functions
*/
-
-int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
+static int cortex_a8_load_core_reg_u32(struct target *target, int num,
armv4_5_mode_t mode, uint32_t * value)
{
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
if ((num <= ARM_CPSR))
{
return ERROR_OK;
}
-int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
+static int cortex_a8_store_core_reg_u32(struct target *target, int num,
armv4_5_mode_t mode, uint32_t value)
{
int retval;
// uint32_t reg;
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
return ERROR_OK;
}
+#endif
-int cortex_a8_read_core_reg(struct target_s *target, int num,
+static int cortex_a8_read_core_reg(struct target *target, int num,
enum armv4_5_mode mode)
{
uint32_t value;
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
+
cortex_a8_dap_read_coreregister_u32(target, &value, num);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return ERROR_OK;
}
-int cortex_a8_write_core_reg(struct target_s *target, int num,
+int cortex_a8_write_core_reg(struct target *target, int num,
enum armv4_5_mode mode, uint32_t value)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
cortex_a8_dap_write_coreregister_u32(target, value, num);
if ((retval = jtag_execute_queue()) != ERROR_OK)
*/
/* Setup hardware Breakpoint Register Pair */
-int cortex_a8_set_breakpoint(struct target_s *target,
- breakpoint_t *breakpoint, uint8_t matchmode)
+static int cortex_a8_set_breakpoint(struct target *target,
+ struct breakpoint *breakpoint, uint8_t matchmode)
{
int retval;
int brp_i=0;
uint32_t control;
uint8_t byte_addr_select = 0x0F;
-
-
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
- cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
if (breakpoint->set)
{
return ERROR_OK;
}
-int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int cortex_a8_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int retval;
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
- cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct cortex_a8_brp * brp_list = cortex_a8->brp_list;
if (!breakpoint->set)
{
return ERROR_OK;
}
-int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+int cortex_a8_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
{
return ERROR_OK;
}
-int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int cortex_a8_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
#if 0
/* It is perfectly possible to remove brakpoints while the taget is running */
* Cortex-A8 Reset fuctions
*/
-int cortex_a8_assert_reset(target_t *target)
+static int cortex_a8_assert_reset(struct target *target)
{
LOG_DEBUG(" ");
armv4_5_invalidate_core_regs(target);
target->state = TARGET_RESET;
-
+
return ERROR_OK;
}
-int cortex_a8_deassert_reset(target_t *target)
+static int cortex_a8_deassert_reset(struct target *target)
{
LOG_DEBUG(" ");
* ap number for every access.
*/
-int cortex_a8_read_memory(struct target_s *target, uint32_t address,
+static int cortex_a8_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
int retval = ERROR_OK;
return retval;
}
-int cortex_a8_write_memory(struct target_s *target, uint32_t address,
+int cortex_a8_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
int retval;
exit(-1);
}
+ if (target->state == TARGET_HALTED)
+ {
/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
/* invalidate I-Cache */
if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
}
+ }
return retval;
}
-int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
+static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
uint32_t count, uint8_t *buffer)
{
return cortex_a8_write_memory(target, address, 4, count, buffer);
}
-int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
+static int cortex_a8_dcc_read(struct swjdp_common *swjdp, uint8_t *value, uint8_t *ctrl)
{
#if 0
u16 dcrdr;
}
-int cortex_a8_handle_target_request(void *priv)
+static int cortex_a8_handle_target_request(void *priv)
{
- target_t *target = priv;
+ struct target *target = priv;
if (!target->type->examined)
return ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
+ struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
if (!target->dbg_msg_enabled)
return ERROR_OK;
* Cortex-A8 target information and configuration
*/
-int cortex_a8_examine(struct target_s *target)
+static int cortex_a8_examine(struct target *target)
{
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
-
+ struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
+ struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
int i;
int retval = ERROR_OK;
uint32_t didr, ctypr, ttypr, cpuid;
LOG_DEBUG("TODO");
-
+
/* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE;
cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
cortex_a8->brp_num_available = cortex_a8->brp_num;
- cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(cortex_a8_brp_t));
+ cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(struct cortex_a8_brp));
// cortex_a8->brb_enabled = ????;
for (i = 0; i < cortex_a8->brp_num; i++)
{
/* Setup Watchpoint Register Pairs */
cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
cortex_a8->wrp_num_available = cortex_a8->wrp_num;
- cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(cortex_a8_wrp_t));
+ cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(struct cortex_a8_wrp));
for (i = 0; i < cortex_a8->wrp_num; i++)
{
cortex_a8->wrp_list[i].used = 0;
/* Configure core debug access */
cortex_a8_init_debug_access(target);
-
+
target->type->examined = 1;
return retval;
* Cortex-A8 target creation and initialization
*/
-void cortex_a8_build_reg_cache(target_t *target)
+static void cortex_a8_build_reg_cache(struct target *target)
{
- reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
- /* get pointers to arch-specific information */
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
+ struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
armv4_5->core_cache = (*cache_p);
}
-int cortex_a8_init_target(struct command_context_s *cmd_ctx,
- struct target_s *target)
+static int cortex_a8_init_target(struct command_context_s *cmd_ctx,
+ struct target *target)
{
cortex_a8_build_reg_cache(target);
return ERROR_OK;
}
-int cortex_a8_init_arch_info(target_t *target,
- cortex_a8_common_t *cortex_a8, jtag_tap_t *tap)
+int cortex_a8_init_arch_info(struct target *target,
+ struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
{
- armv4_5_common_t *armv4_5;
- armv7a_common_t *armv7a;
+ struct arm *armv4_5;
+ struct armv7a_common *armv7a;
armv7a = &cortex_a8->armv7a_common;
armv4_5 = &armv7a->armv4_5_common;
- swjdp_common_t *swjdp = &armv7a->swjdp_info;
+ struct swjdp_common *swjdp = &armv7a->swjdp_info;
- /* Setup cortex_a8_common_t */
+ /* Setup struct cortex_a8_common */
cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
- cortex_a8->arch_info = NULL;
- armv7a->arch_info = cortex_a8;
armv4_5->arch_info = armv7a;
armv4_5_init_arch_info(target, armv4_5);
/* register arch-specific functions */
armv7a->examine_debug_reason = NULL;
- armv7a->pre_debug_entry = NULL;
armv7a->post_debug_entry = cortex_a8_post_debug_entry;
armv7a->pre_restore_context = NULL;
return ERROR_OK;
}
-int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
+static int cortex_a8_target_create(struct target *target, Jim_Interp *interp)
{
- cortex_a8_common_t *cortex_a8 = calloc(1, sizeof(cortex_a8_common_t));
+ struct cortex_a8_common *cortex_a8 = calloc(1, sizeof(struct cortex_a8_common));
cortex_a8_init_arch_info(target, cortex_a8, target->tap);
return ERROR_OK;
}
-static int cortex_a8_handle_cache_info_command(struct command_context_s *cmd_ctx,
- char *cmd, char **args, int argc)
+COMMAND_HANDLER(cortex_a8_handle_cache_info_command)
{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5 = target->arch_info;
- armv7a_common_t *armv7a = armv4_5->arch_info;
+ struct target *target = get_current_target(cmd_ctx);
+ struct armv7a_common *armv7a = target_to_armv7a(target);
return armv4_5_handle_cache_info_command(cmd_ctx,
&armv7a->armv4_5_mmu.armv4_5_cache);
}
-static int cortex_a8_handle_dbginit_command(struct command_context_s *cmd_ctx,
- char *cmd, char **args, int argc)
+COMMAND_HANDLER(cortex_a8_handle_dbginit_command)
{
- target_t *target = get_current_target(cmd_ctx);
+ struct target *target = get_current_target(cmd_ctx);
cortex_a8_init_debug_access(target);
}
-int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
+static int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
{
command_t *cortex_a8_cmd;
int retval = ERROR_OK;
return retval;
}
+
+struct target_type cortexa8_target = {
+ .name = "cortex_a8",
+
+ .poll = cortex_a8_poll,
+ .arch_state = armv7a_arch_state,
+
+ .target_request_data = NULL,
+
+ .halt = cortex_a8_halt,
+ .resume = cortex_a8_resume,
+ .step = cortex_a8_step,
+
+ .assert_reset = cortex_a8_assert_reset,
+ .deassert_reset = cortex_a8_deassert_reset,
+ .soft_reset_halt = NULL,
+
+ .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+ .read_memory = cortex_a8_read_memory,
+ .write_memory = cortex_a8_write_memory,
+ .bulk_write_memory = cortex_a8_bulk_write_memory,
+ .checksum_memory = arm7_9_checksum_memory,
+ .blank_check_memory = arm7_9_blank_check_memory,
+
+ .run_algorithm = armv4_5_run_algorithm,
+
+ .add_breakpoint = cortex_a8_add_breakpoint,
+ .remove_breakpoint = cortex_a8_remove_breakpoint,
+ .add_watchpoint = NULL,
+ .remove_watchpoint = NULL,
+
+ .register_commands = cortex_a8_register_commands,
+ .target_create = cortex_a8_target_create,
+ .init_target = cortex_a8_init_target,
+ .examine = cortex_a8_examine,
+ .mrc = cortex_a8_mrc,
+ .mcr = cortex_a8_mcr,
+};
projects / fw / openocd / blobdiff