static int cortex_a_prep_memaccess(struct target *target, int phys_access)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
int mmu_enabled = 0;
if (phys_access == 0) {
cortex_a_mmu(target, &mmu_enabled);
if (mmu_enabled)
cortex_a_mmu_modify(target, 1);
+ if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
+ /* overwrite DACR to all-manager */
+ armv7a->arm.mcr(target, 15,
+ 0, 0, 3, 0,
+ 0xFFFFFFFF);
+ }
} else {
cortex_a_mmu(target, &mmu_enabled);
if (mmu_enabled)
static int cortex_a_post_memaccess(struct target *target, int phys_access)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
if (phys_access == 0) {
+ if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
+ /* restore */
+ armv7a->arm.mcr(target, 15,
+ 0, 0, 3, 0,
+ cortex_a->cp15_dacr_reg);
+ }
dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
} else {
int mmu_enabled = 0;
static int cortex_a8_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
LOG_DEBUG(" ");
/* Unlocking the debug registers for modification
* The debugport might be uninitialised so try twice */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval != ERROR_OK) {
/* try again */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
if (retval == ERROR_OK)
LOG_USER(
static int cortex_a_init_debug_access(struct target *target)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
uint32_t dbg_osreg;
uint32_t cortex_part_num;
switch (cortex_part_num) {
case CORTEX_A7_PARTNUM:
case CORTEX_A15_PARTNUM:
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLSR,
&dbg_osreg);
if (retval != ERROR_OK)
if (dbg_osreg & CPUDBG_OSLAR_LK_MASK)
/* Unlocking the DEBUG OS registers for modification */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
break;
return retval;
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg);
return retval;
/* Disable cacheline fills and force cache write-through in debug state */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCCR, 0);
if (retval != ERROR_OK)
return retval;
/* Disable TLB lookup and refill/eviction in debug state */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSMCR, 0);
if (retval != ERROR_OK)
return retval;
* Writes final value of DSCR into *dscr. Pass force to force always
* reading DSCR at least once. */
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while ((*dscr & DSCR_INSTR_COMP) == 0 || force) {
force = false;
- int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK) {
LOG_ERROR("Could not read DSCR register");
uint32_t dscr;
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
dscr = dscr_p ? *dscr_p : 0;
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, opcode);
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
do {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK) {
LOG_ERROR("Could not read DSCR register");
{
int retval = ERROR_OK;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
retval = cortex_a_dap_read_coreregister_u32(target, regfile, 0);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap->ap_num,
+ retval = mem_ap_read_buf(armv7a->memory_ap,
(uint8_t *)(®file[1]), 4, 15, address);
return retval;
uint8_t reg = regnum&0xFF;
uint32_t dscr = 0;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
if (reg > 17)
return retval;
}
/* Wait for DTRRXfull then read DTRRTX */
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
}
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, value);
LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
uint8_t Rd = regnum&0xFF;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
LOG_DEBUG("write DCC 0x%08" PRIx32, value);
- retval = mem_ap_sel_write_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, value);
if (retval != ERROR_OK)
return retval;
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num, address, value);
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap, address, value);
return retval;
}
static int cortex_a_write_dcc(struct cortex_a_common *a, uint32_t data)
{
LOG_DEBUG("write DCC 0x%08" PRIx32, data);
- return mem_ap_sel_write_u32(a->armv7a_common.arm.dap,
- a->armv7a_common.debug_ap->ap_num, a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+ return mem_ap_write_u32(a->armv7a_common.debug_ap,
+ a->armv7a_common.debug_base + CPUDBG_DTRRX, data);
}
static int cortex_a_read_dcc(struct cortex_a_common *a, uint32_t *data,
uint32_t *dscr_p)
{
- struct adiv5_dap *swjdp = a->armv7a_common.arm.dap;
uint32_t dscr = DSCR_INSTR_COMP;
int retval;
dscr = *dscr_p;
/* Wait for DTRRXfull */
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) == 0) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
}
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
static int cortex_a_dpm_prepare(struct arm_dpm *dpm)
{
struct cortex_a_common *a = dpm_to_a(dpm);
- struct adiv5_dap *swjdp = a->armv7a_common.arm.dap;
uint32_t dscr;
int retval;
/* set up invariant: INSTR_COMP is set after ever DPM operation */
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
for (;; ) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, a->armv7a_common.debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(a->armv7a_common.debug_ap,
a->armv7a_common.debug_base + CPUDBG_DSCR,
&dscr);
if (retval != ERROR_OK)
uint32_t dscr;
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = &cortex_a->armv7a_common;
- struct adiv5_dap *swjdp = armv7a->arm.dap;
enum target_state prev_target_state = target->state;
/* toggle to another core is done by gdb as follow */
/* maint packet J core_id */
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
return retval;
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
int retval = ERROR_OK;
uint32_t dscr;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
/*
* Tell the core to be halted by writing DRCR with 0x1
* and then wait for the core to be halted.
*/
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_HALT);
if (retval != ERROR_OK)
return retval;
/*
* enter halting debug mode
*/
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
for (;; ) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
buf_set_u32(arm->pc->value, 0, 32, resume_pc);
arm->pc->dirty = 1;
arm->pc->valid = 1;
+
/* restore dpm_mode at system halt */
dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
/* called it now before restoring context because it uses cpu
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
- struct adiv5_dap *swjdp = arm->dap;
int retval;
uint32_t dscr;
/*
* disable IRQs by default, with optional override...
*/
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
if ((dscr & DSCR_INSTR_COMP) == 0)
LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr & ~DSCR_ITR_EN);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_RESTART |
DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
for (;; ) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
- struct adiv5_dap *swjdp = armv7a->arm.dap;
struct reg *reg;
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a->cpudbg_dscr);
/* REVISIT surely we should not re-read DSCR !! */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
/* Enable the ITR execution once we are in debug mode */
dscr |= DSCR_ITR_EN;
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK)
return retval;
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
uint32_t wfar;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_WFAR,
&wfar);
if (retval != ERROR_OK)
(cortex_a->cp15_control_reg & 0x1000U) ? 1 : 0;
cortex_a->curr_mode = armv7a->arm.core_mode;
+ /* switch to SVC mode to read DACR */
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
+ armv7a->arm.mrc(target, 15,
+ 0, 0, 3, 0,
+ &cortex_a->cp15_dacr_reg);
+
+ LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32,
+ cortex_a->cp15_dacr_reg);
+
+ dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
return ERROR_OK;
}
int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
uint32_t dscr;
/* Read DSCR */
- int retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ int retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (ERROR_OK != retval)
return retval;
dscr |= value & bit_mask;
/* write new DSCR */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
return retval;
}
if (retval != ERROR_OK)
return retval;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
while (target->state != TARGET_HALTED) {
retval = cortex_a_poll(target);
if (retval != ERROR_OK)
uint32_t new_dscr = (*dscr & ~DSCR_EXT_DCC_MASK) | mode;
if (new_dscr != *dscr) {
struct armv7a_common *armv7a = target_to_armv7a(target);
- int retval = mem_ap_sel_write_atomic_u32(armv7a->arm.dap,
- armv7a->debug_ap->ap_num, armv7a->debug_base + CPUDBG_DSCR, new_dscr);
+ int retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_DSCR, new_dscr);
if (retval == ERROR_OK)
*dscr = new_dscr;
return retval;
{
/* Waits until the specified bit(s) of DSCR take on a specified value. */
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
- long long then = timeval_ms();
+ int64_t then = timeval_ms();
int retval;
while ((*dscr & mask) != value) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, dscr);
if (retval != ERROR_OK)
return retval;
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
/* Move from coprocessor to R0. */
retval = cortex_a_exec_opcode(target, opcode, dscr);
return retval;
/* Read the value transferred to DTRTX. */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, data);
if (retval != ERROR_OK)
return retval;
{
int retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
/* Write the value into DTRRX. */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, data);
if (retval != ERROR_OK)
return retval;
* - R0 is marked dirty.
*/
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
struct arm *arm = &armv7a->arm;
int retval;
data = target_buffer_get_u16(target, buffer);
else
data = target_buffer_get_u32(target, buffer);
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, data);
if (retval != ERROR_OK)
return retval;
* - R0 is marked dirty.
*/
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
/* Switch to fast mode if not already in that mode. */
return retval;
/* Latch STC instruction. */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, ARMV4_5_STC(0, 1, 0, 1, 14, 5, 0, 4));
if (retval != ERROR_OK)
return retval;
/* Transfer all the data and issue all the instructions. */
- return mem_ap_sel_write_buf_noincr(swjdp, armv7a->debug_ap->ap_num, buffer,
+ return mem_ap_write_buf_noincr(armv7a->debug_ap, buffer,
4, count, armv7a->debug_base + CPUDBG_DTRRX);
}
/* Write memory through APB-AP. */
int retval, final_retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
struct arm *arm = &armv7a->arm;
uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
return ERROR_OK;
/* Clear any abort. */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
/* Read DSCR. */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
goto out;
/* Get the memory address into R0. */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, address);
if (retval != ERROR_OK)
goto out;
/* Wait until DTRRX is empty (according to ARMv7-A/-R architecture manual
* section C8.4.3, checking InstrCmpl_l is not sufficient; one must also
* check RXfull_l). Most of the time this will be free because RXfull_l
- * will be cleared immediately and cached in dscr. However, don’t do this
+ * will be cleared immediately and cached in dscr. However, don't do this
* if there is fault, because then the instruction might not have completed
* successfully. */
if (!(dscr & DSCR_STICKY_ABORT_PRECISE)) {
/* If there were any sticky abort flags, clear them. */
if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
fault_dscr = dscr;
- mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
} else {
/* If the DCC is nonempty, clear it. */
if (dscr & DSCR_DTRTX_FULL_LATCHED) {
uint32_t dummy;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &dummy);
if (final_retval == ERROR_OK)
final_retval = retval;
* - R0 is marked dirty.
*/
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
struct arm *arm = &armv7a->arm;
int retval;
return retval;
/* Read the value transferred to DTRTX into the buffer. */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &data);
if (retval != ERROR_OK)
return retval;
* - R0 is marked dirty.
*/
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
uint32_t u32;
int retval;
return retval;
/* Latch LDC instruction. */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_ITR, ARMV4_5_LDC(0, 1, 0, 1, 14, 5, 0, 4));
if (retval != ERROR_OK)
return retval;
* memory. The last read of DTRTX in this call reads the second-to-last
* word from memory and issues the read instruction for the last word.
*/
- retval = mem_ap_sel_read_buf_noincr(swjdp, armv7a->debug_ap->ap_num, buffer,
+ retval = mem_ap_read_buf_noincr(armv7a->debug_ap, buffer,
4, count, armv7a->debug_base + CPUDBG_DTRTX);
if (retval != ERROR_OK)
return retval;
/* Read the value transferred to DTRTX into the buffer. This is the last
* word. */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &u32);
if (retval != ERROR_OK)
return retval;
/* Read memory through APB-AP. */
int retval, final_retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
struct arm *arm = &armv7a->arm;
uint32_t dscr, orig_dfar, orig_dfsr, fault_dscr, fault_dfar, fault_dfsr;
return ERROR_OK;
/* Clear any abort. */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
if (retval != ERROR_OK)
return retval;
/* Read DSCR */
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
goto out;
/* Get the memory address into R0. */
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRRX, address);
if (retval != ERROR_OK)
goto out;
/* If there were any sticky abort flags, clear them. */
if (dscr & (DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE)) {
fault_dscr = dscr;
- mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DRCR, DRCR_CLEAR_EXCEPTIONS);
dscr &= ~(DSCR_STICKY_ABORT_PRECISE | DSCR_STICKY_ABORT_IMPRECISE);
} else {
/* If the DCC is nonempty, clear it. */
if (dscr & DSCR_DTRTX_FULL_LATCHED) {
uint32_t dummy;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &dummy);
if (final_retval == ERROR_OK)
final_retval = retval;
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
- retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap->ap_num, buffer, size, count, address);
+ retval = mem_ap_read_buf(armv7a->memory_ap, buffer, size, count, address);
return retval;
}
if (!count || !buffer)
return ERROR_COMMAND_SYNTAX_ERROR;
- retval = mem_ap_sel_write_buf(swjdp, armv7a->memory_ap->ap_num, buffer, size, count, address);
+ retval = mem_ap_write_buf(armv7a->memory_ap, buffer, size, count, address);
return retval;
}
{
struct target *target = priv;
struct armv7a_common *armv7a = target_to_armv7a(target);
- struct adiv5_dap *swjdp = armv7a->arm.dap;
int retval;
if (!target_was_examined(target))
if (target->state == TARGET_RUNNING) {
uint32_t request;
uint32_t dscr;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
/* check if we have data */
+ int64_t then = timeval_ms();
while ((dscr & DSCR_DTR_TX_FULL) && (retval == ERROR_OK)) {
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DTRTX, &request);
if (retval == ERROR_OK) {
target_request(target, request);
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCR, &dscr);
}
+ if (timeval_ms() > then + 1000) {
+ LOG_ERROR("Timeout waiting for dtr tx full");
+ return ERROR_FAIL;
+ }
}
}
int retval = ERROR_OK;
uint32_t didr, ctypr, ttypr, cpuid, dbg_osreg;
+ retval = dap_dp_init(swjdp);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not initialize the debug port");
+ return retval;
+ }
+
/* Search for the APB-AB - it is needed for access to debug registers */
retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
if (retval != ERROR_OK) {
return retval;
}
- /* We do one extra read to ensure DAP is configured,
- * we call ahbap_debugport_init(swjdp) instead
- */
- retval = ahbap_debugport_init(swjdp, armv7a->debug_ap->ap_num);
- if (retval != ERROR_OK)
+ retval = mem_ap_init(armv7a->debug_ap);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not initialize the APB-AP");
return retval;
+ }
+
+ armv7a->debug_ap->memaccess_tck = 80;
- /* Search for the AHB-AB */
+ /* Search for the AHB-AB.
+ * REVISIT: We should search for AXI-AP as well and make sure the AP's MEMTYPE says it
+ * can access system memory. */
+ armv7a->memory_ap_available = false;
retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv7a->memory_ap);
- if (retval != ERROR_OK) {
+ if (retval == ERROR_OK) {
+ retval = mem_ap_init(armv7a->memory_ap);
+ if (retval == ERROR_OK)
+ armv7a->memory_ap_available = true;
+ else
+ LOG_WARNING("Could not initialize AHB-AP for memory access - using APB-AP");
+ } else {
/* AHB-AP not found - use APB-AP */
LOG_DEBUG("Could not find AHB-AP - using APB-AP for memory access");
- armv7a->memory_ap_available = false;
- } else {
- armv7a->memory_ap_available = true;
}
-
if (!target->dbgbase_set) {
uint32_t dbgbase;
/* Get ROM Table base */
int32_t coreidx = target->coreid;
LOG_DEBUG("%s's dbgbase is not set, trying to detect using the ROM table",
target->cmd_name);
- retval = dap_get_debugbase(swjdp, 1, &dbgbase, &apid);
+ retval = dap_get_debugbase(armv7a->debug_ap, &dbgbase, &apid);
if (retval != ERROR_OK)
return retval;
/* Lookup 0x15 -- Processor DAP */
- retval = dap_lookup_cs_component(swjdp, 1, dbgbase, 0x15,
+ retval = dap_lookup_cs_component(armv7a->debug_ap, dbgbase, 0x15,
&armv7a->debug_base, &coreidx);
if (retval != ERROR_OK) {
LOG_ERROR("Can't detect %s's dbgbase from the ROM table; you need to specify it explicitly.",
} else
armv7a->debug_base = target->dbgbase;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_CPUID, &cpuid);
if (retval != ERROR_OK)
return retval;
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_CPUID, &cpuid);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "CPUID");
return retval;
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_CTYPR, &ctypr);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "CTYPR");
return retval;
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_TTYPR, &ttypr);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "TTYPR");
return retval;
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DIDR, &didr);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "DIDR");
if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
CORTEX_A15_PARTNUM) {
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
if ((cpuid & CORTEX_A_MIDR_PARTNUM_MASK) >> CORTEX_A_MIDR_PARTNUM_SHIFT ==
CORTEX_A7_PARTNUM) {
- retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_write_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_OSLAR,
0);
return retval;
}
- retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap->ap_num,
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg);
if (retval != ERROR_OK)
LOG_DEBUG("Configured %i hw breakpoints", cortex_a->brp_num);
+ /* select debug_ap as default */
+ swjdp->apsel = armv7a->debug_ap->ap_num;
+
target_set_examined(target);
return ERROR_OK;
}
tap->dap->tap = tap;
}
- tap->dap->ap[dap_ap_get_select(tap->dap)].memaccess_tck = 80;
armv7a->arm.dap = tap->dap;
cortex_a->fast_reg_read = 0;
return ERROR_OK;
}
+COMMAND_HANDLER(handle_cortex_a_dacrfixup_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct cortex_a_common *cortex_a = target_to_cortex_a(target);
+
+ static const Jim_Nvp nvp_dacrfixup_modes[] = {
+ { .name = "off", .value = CORTEX_A_DACRFIXUP_OFF },
+ { .name = "on", .value = CORTEX_A_DACRFIXUP_ON },
+ { .name = NULL, .value = -1 },
+ };
+ const Jim_Nvp *n;
+
+ if (CMD_ARGC > 0) {
+ n = Jim_Nvp_name2value_simple(nvp_dacrfixup_modes, CMD_ARGV[0]);
+ if (n->name == NULL)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ cortex_a->dacrfixup_mode = n->value;
+
+ }
+
+ n = Jim_Nvp_value2name_simple(nvp_dacrfixup_modes, cortex_a->dacrfixup_mode);
+ command_print(CMD_CTX, "cortex_a domain access control fixup %s", n->name);
+
+ return ERROR_OK;
+}
+
static const struct command_registration cortex_a_exec_command_handlers[] = {
{
.name = "cache_info",
.help = "mask cortex_a interrupts",
.usage = "['on'|'off']",
},
-
+ {
+ .name = "dacrfixup",
+ .handler = handle_cortex_a_dacrfixup_command,
+ .mode = COMMAND_EXEC,
+ .help = "set domain access control (DACR) to all-manager "
+ "on memory access",
+ .usage = "['on'|'off']",
+ },
COMMAND_REGISTRATION_DONE
};
projects / fw / openocd / blobdiff