armv7m_trace: get rid of the old tpiu code

[fw/openocd] / src / target / cortex_a.c

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index f71b1552418aad0b9d928b82d5fc7b896d9d2d3f..d27c298b64ab9f0540a9500631cc6de47e1b919e 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -841,7 +841,7 @@ static int cortex_a_internal_restore(struct target *target, int current,
                        LOG_ERROR("How do I resume into Jazelle state??");
                        return ERROR_FAIL;
                case ARM_STATE_AARCH64:
-                       LOG_ERROR("Shoudn't be in AARCH64 state");
+                       LOG_ERROR("Shouldn't be in AARCH64 state");
                        return ERROR_FAIL;
        }
        LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
@@ -1115,7 +1115,8 @@ static int cortex_a_post_debug_entry(struct target *target)
        return ERROR_OK;
 }
 
-int cortex_a_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value)
+static int cortex_a_set_dscr_bits(struct target *target,
+               unsigned long bit_mask, unsigned long value)
 {
        struct armv7a_common *armv7a = target_to_armv7a(target);
        uint32_t dscr;
@@ -1680,10 +1681,10 @@ static int cortex_a_assert_reset(struct target *target)
                 */
 
                /*
-                * FIXME: fix reset when transport is SWD. This is a temporary
+                * FIXME: fix reset when transport is not JTAG. This is a temporary
                 * work-around for release v0.10 that is not intended to stay!
                 */
-               if (transport_is_swd() ||
+               if (!transport_is_jtag() ||
                                (target->reset_halt && (jtag_get_reset_config() & RESET_SRST_NO_GATING)))
                        adapter_assert_reset();
 
@@ -2498,7 +2499,7 @@ static int cortex_a_read_phys_memory(struct target *target,
        if (!count || !buffer)
                return ERROR_COMMAND_SYNTAX_ERROR;
 
-       LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+       LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
                address, size, count);
 
        /* read memory through the CPU */
@@ -2515,7 +2516,7 @@ static int cortex_a_read_memory(struct target *target, target_addr_t address,
        int retval;
 
        /* cortex_a handles unaligned memory access */
-       LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+       LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
                address, size, count);
 
        cortex_a_prep_memaccess(target, 0);
@@ -2534,7 +2535,7 @@ static int cortex_a_write_phys_memory(struct target *target,
        if (!count || !buffer)
                return ERROR_COMMAND_SYNTAX_ERROR;
 
-       LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+       LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
                address, size, count);
 
        /* write memory through the CPU */
@@ -2551,7 +2552,7 @@ static int cortex_a_write_memory(struct target *target, target_addr_t address,
        int retval;
 
        /* cortex_a handles unaligned memory access */
-       LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+       LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
                address, size, count);
 
        /* memory writes bypass the caches, must flush before writing */
@@ -2959,6 +2960,7 @@ static void cortex_a_deinit_target(struct target *target)
        }
 
        free(cortex_a->brp_list);
+       arm_free_reg_cache(dpm->arm);
        free(dpm->dbp);
        free(dpm->dwp);
        free(target->private_config);