1, 0, /* CRn, CRm */
cortex_a8->cp15_control_reg);
}
- return ERROR_OK;
+ return retval;
}
/* check address before cortex_a8_apb read write access with mmu on
/* called it now before restoring context because it uses cpu
* register r0 for restoring cp15 control register */
retval = cortex_a8_restore_cp15_control_reg(target);
+ if (retval != ERROR_OK)
+ return retval;
retval = cortex_a8_restore_context(target, handle_breakpoints);
if (retval != ERROR_OK)
return retval;
cortex_a8_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
if (target->smp)
{ target->gdb_service->core[0] = -1;
- retval += cortex_a8_restore_smp(target, handle_breakpoints);
+ retval = cortex_a8_restore_smp(target, handle_breakpoints);
+ if (retval != ERROR_OK)
+ return retval;
}
cortex_a8_internal_restart(target);
/* write memory through APB-AP */
- int retval = ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *armv4_5 = &armv7a->armv4_5_common;
int total_bytes = count * size;
/* read memory through APB-AP */
- int retval = ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *armv4_5 = &armv7a->armv4_5_common;
int total_bytes = count * size;
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
- int retval = ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
uint8_t apsel = swjdp->apsel;
LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d",
address, size, count);
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap;
- int retval = ERROR_INVALID_ARGUMENTS;
+ int retval = ERROR_COMMAND_SYNTAX_ERROR;
uint8_t apsel = swjdp->apsel;
LOG_DEBUG("Writing memory to real address 0x%x; size %d; count %d", address,
.handler = cortex_a8_handle_cache_info_command,
.mode = COMMAND_EXEC,
.help = "display information about target caches",
+ .usage = "",
},
{
.name = "dbginit",
.handler = cortex_a8_handle_dbginit_command,
.mode = COMMAND_EXEC,
.help = "Initialize core debug",
+ .usage = "",
},
{ .name ="smp_off",
.handler = cortex_a8_handle_smp_off_command,
.mode = COMMAND_EXEC,
.help = "Stop smp handling",
+ .usage = "",
},
{
.name ="smp_on",
.handler = cortex_a8_handle_smp_on_command,
.mode = COMMAND_EXEC,
.help = "Restart smp handling",
+ .usage = "",
},
{
.name ="smp_gdb",
.handler = cortex_a8_handle_smp_gdb_command,
.mode = COMMAND_EXEC,
.help = "display/fix current core played to gdb",
+ .usage = "",
},
.name = "cortex_a8",
.mode = COMMAND_ANY,
.help = "Cortex-A8 command group",
+ .usage = "",
.chain = cortex_a8_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE