cortex_a: do not try to use MMU for translation if it wasn't enabled on target stop

[fw/openocd] / src / target / cortex_a.c

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 85f22474a7c2cf4152779396bde17481a70090fe..5e37e2a3323cd42c70d703c9f1f5b7390777a5b6 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -279,8 +279,8 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
        if (retval != ERROR_OK)
                return retval;
 
-       retval = mem_ap_sel_read_buf_u32(swjdp, armv7a->memory_ap,
-                       (uint8_t *)(&regfile[1]), 4*15, address);
+       retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap,
+                       (uint8_t *)(&regfile[1]), 4, 15, address);
 
        return retval;
 }
@@ -1891,8 +1891,8 @@ static int cortex_a8_write_apb_ab_memory(struct target *target,
                goto error_unset_dtr_w;
 
        /* Do the write */
-       retval = mem_ap_sel_write_buf_u32_noincr(swjdp, armv7a->debug_ap,
-                                       tmp_buff, (total_u32)<<2, armv7a->debug_base + CPUDBG_DTRRX);
+       retval = mem_ap_sel_write_buf_noincr(swjdp, armv7a->debug_ap,
+                                       tmp_buff, 4, total_u32, armv7a->debug_base + CPUDBG_DTRRX);
        if (retval != ERROR_OK)
                goto error_unset_dtr_w;
 
@@ -2011,7 +2011,7 @@ static int cortex_a8_read_apb_ab_memory(struct target *target,
        dscr = (dscr & ~DSCR_EXT_DCC_MASK) | DSCR_EXT_DCC_FAST_MODE;
        buff32[1] = dscr;
        /*  group the 2 access CPUDBG_ITR 0x84 and CPUDBG_DSCR 0x88 */
-       retval += mem_ap_sel_write_buf_u32(swjdp, armv7a->debug_ap, (uint8_t *)buff32, 8,
+       retval += mem_ap_sel_write_buf(swjdp, armv7a->debug_ap, (uint8_t *)buff32, 4, 2,
                        armv7a->debug_base + CPUDBG_ITR);
        if (retval != ERROR_OK)
                goto error_unset_dtr_r;
@@ -2025,7 +2025,7 @@ static int cortex_a8_read_apb_ab_memory(struct target *target,
                 *
                 * This data is read in aligned to 32 bit boundary, hence may need shifting later.
                 */
-               retval = mem_ap_sel_read_buf_u32_noincr(swjdp, armv7a->debug_ap, (uint8_t *)tmp_buff, (total_u32-1) * 4,
+               retval = mem_ap_sel_read_buf_noincr(swjdp, armv7a->debug_ap, (uint8_t *)tmp_buff, 4, total_u32 - 1,
                                                                        armv7a->debug_base + CPUDBG_DTRTX);
                if (retval != ERROR_OK)
                        goto error_unset_dtr_r;
@@ -2112,21 +2112,7 @@ static int cortex_a8_read_phys_memory(struct target *target,
                if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
 
                        /* read memory through AHB-AP */
-
-                       switch (size) {
-                               case 4:
-                                       retval = mem_ap_sel_read_buf_u32(swjdp, armv7a->memory_ap,
-                                               buffer, 4 * count, address);
-                                       break;
-                               case 2:
-                                       retval = mem_ap_sel_read_buf_u16(swjdp, armv7a->memory_ap,
-                                               buffer, 2 * count, address);
-                                       break;
-                               case 1:
-                                       retval = mem_ap_sel_read_buf_u8(swjdp, armv7a->memory_ap,
-                                               buffer, count, address);
-                                       break;
-                       }
+                       retval = mem_ap_sel_read_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
                } else {
 
                        /* read memory through APB-AP */
@@ -2145,7 +2131,7 @@ static int cortex_a8_read_phys_memory(struct target *target,
 static int cortex_a8_read_memory(struct target *target, uint32_t address,
        uint32_t size, uint32_t count, uint8_t *buffer)
 {
-       int enabled = 0;
+       int mmu_enabled = 0;
        uint32_t virt, phys;
        int retval;
        struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -2155,31 +2141,32 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address,
        /* cortex_a8 handles unaligned memory access */
        LOG_DEBUG("Reading memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
                size, count);
+
+       /* determine if MMU was enabled on target stop */
+       if (!armv7a->is_armv7r) {
+               retval = cortex_a8_mmu(target, &mmu_enabled);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
+
        if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
-               if (!armv7a->is_armv7r) {
-                       retval = cortex_a8_mmu(target, &enabled);
+               if (mmu_enabled) {
+                       virt = address;
+                       retval = cortex_a8_virt2phys(target, virt, &phys);
                        if (retval != ERROR_OK)
                                return retval;
 
-
-                       if (enabled) {
-                               virt = address;
-                               retval = cortex_a8_virt2phys(target, virt, &phys);
-                               if (retval != ERROR_OK)
-                                       return retval;
-
-                               LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
-                                       virt, phys);
-                               address = phys;
-                       }
+                       LOG_DEBUG("Reading at virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
+                                 virt, phys);
+                       address = phys;
                }
                retval = cortex_a8_read_phys_memory(target, address, size, count, buffer);
        } else {
-               if (!armv7a->is_armv7r) {
+               if (mmu_enabled) {
                        retval = cortex_a8_check_address(target, address);
                        if (retval != ERROR_OK)
                                return retval;
-                       /*  enable mmu */
+                       /* enable MMU as we could have disabled it for phys access */
                        retval = cortex_a8_mmu_modify(target, 1);
                        if (retval != ERROR_OK)
                                return retval;
@@ -2206,22 +2193,7 @@ static int cortex_a8_write_phys_memory(struct target *target,
                if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
 
                        /* write memory through AHB-AP */
-
-                       switch (size) {
-                               case 4:
-                                       retval = mem_ap_sel_write_buf_u32(swjdp, armv7a->memory_ap,
-                                               buffer, 4 * count, address);
-                                       break;
-                               case 2:
-                                       retval = mem_ap_sel_write_buf_u16(swjdp, armv7a->memory_ap,
-                                               buffer, 2 * count, address);
-                                       break;
-                               case 1:
-                                       retval = mem_ap_sel_write_buf_u8(swjdp, armv7a->memory_ap,
-                                               buffer, count, address);
-                                       break;
-                       }
-
+                       retval = mem_ap_sel_write_buf(swjdp, armv7a->memory_ap, buffer, size, count, address);
                } else {
 
                        /* write memory through APB-AP */
@@ -2295,44 +2267,46 @@ static int cortex_a8_write_phys_memory(struct target *target,
 static int cortex_a8_write_memory(struct target *target, uint32_t address,
        uint32_t size, uint32_t count, const uint8_t *buffer)
 {
-       int enabled = 0;
+       int mmu_enabled = 0;
        uint32_t virt, phys;
        int retval;
        struct armv7a_common *armv7a = target_to_armv7a(target);
        struct adiv5_dap *swjdp = armv7a->arm.dap;
        uint8_t apsel = swjdp->apsel;
+
        /* cortex_a8 handles unaligned memory access */
        LOG_DEBUG("Writing memory at address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address,
                size, count);
-       if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
 
+       /* determine if MMU was enabled on target stop */
+       if (!armv7a->is_armv7r) {
+               retval = cortex_a8_mmu(target, &mmu_enabled);
+               if (retval != ERROR_OK)
+                       return retval;
+       }
+
+       if (armv7a->memory_ap_available && (apsel == armv7a->memory_ap)) {
                LOG_DEBUG("Writing memory to address 0x%" PRIx32 "; size %" PRId32 "; count %" PRId32, address, size,
                        count);
-               if (!armv7a->is_armv7r) {
-                       retval = cortex_a8_mmu(target, &enabled);
+               if (mmu_enabled) {
+                       virt = address;
+                       retval = cortex_a8_virt2phys(target, virt, &phys);
                        if (retval != ERROR_OK)
                                return retval;
 
-                       if (enabled) {
-                               virt = address;
-                               retval = cortex_a8_virt2phys(target, virt, &phys);
-                               if (retval != ERROR_OK)
-                                       return retval;
-                               LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
-                                       virt,
-                                       phys);
-                               address = phys;
-                       }
+                       LOG_DEBUG("Writing to virtual address. Translating v:0x%" PRIx32 " to r:0x%" PRIx32,
+                                 virt,
+                                 phys);
+                       address = phys;
                }
-
                retval = cortex_a8_write_phys_memory(target, address, size,
                                count, buffer);
        } else {
-               if (!armv7a->is_armv7r) {
+               if (mmu_enabled) {
                        retval = cortex_a8_check_address(target, address);
                        if (retval != ERROR_OK)
                                return retval;
-                       /*  enable mmu  */
+                       /* enable MMU as we could have disabled it for phys access */
                        retval = cortex_a8_mmu_modify(target, 1);
                        if (retval != ERROR_OK)
                                return retval;