target: armv8: Avoid semihosting segfault on halt

[fw/openocd] / src / target / armv8_opcodes.h

diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index 2d8ddd82479fb3def99152fddb8efd11668bec7a..3fda29668a27dac00376d34d08198db0249f4dfa 100644 (file)
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -159,6 +159,22 @@
 #define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
 #define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
 
+#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd)
+#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd)
+#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd)
+
+#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd)
+#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
+#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
+
+#define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd)
+#define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd)
+
+#define ARMV8_MRS_FPCR(Rt)     (0xd53b4400 | (Rt))
+#define ARMV8_MRS_FPSR(Rt)     (0xd53b4420 | (Rt))
+#define ARMV8_MSR_FPCR(Rt)     (0xd51b4400 | (Rt))
+#define ARMV8_MSR_FPSR(Rt)     (0xd51b4420 | (Rt))
+
 #define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
 
 enum armv8_opcode {
@@ -180,6 +196,12 @@ enum armv8_opcode {
        ARMV8_OPC_DCCIVAC,
        ARMV8_OPC_ICIVAU,
        ARMV8_OPC_HLT,
+       ARMV8_OPC_STRB_IP,
+       ARMV8_OPC_STRH_IP,
+       ARMV8_OPC_STRW_IP,
+       ARMV8_OPC_LDRB_IP,
+       ARMV8_OPC_LDRH_IP,
+       ARMV8_OPC_LDRW_IP,
        ARMV8_OPC_NUM,
 };