Use boolean argument for register_get_by_name()

[fw/openocd] / src / target / armv8_opcodes.h

diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index cb20c84a966a4bf57bd59426eda5dec4497ba568..239c4c5f1807d3cd65977bb1e3cee5f9d92595e7 100644 (file)
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -17,11 +17,6 @@
 
 #include "arm_opcodes.h"
 
-/* ARM V8 Move from system register to general purpose register
- * R = 1: SPSR R = 0: CPSR
- * Rn: target register
- */
-#define SYSTEM_CUREL                   0b1100001000010010
 #define SYSTEM_CUREL_MASK              0xC0
 #define SYSTEM_CUREL_SHIFT             6
 #define SYSTEM_CUREL_EL0               0x0
@@ -47,6 +42,10 @@
 #define SYSTEM_ELR_EL2                 0b1110001000000001
 #define SYSTEM_ELR_EL3                 0b1111001000000001
 
+#define SYSTEM_SCTLR_EL1       0b1100000010000000
+#define SYSTEM_SCTLR_EL2       0b1110000010000000
+#define SYSTEM_SCTLR_EL3       0b1111000010000000
+
 #define SYSTEM_FPCR                    0b1101101000100000
 #define SYSTEM_FPSR                    0b1101101000100001
 #define SYSTEM_DAIF                    0b1101101000010001
@@ -125,12 +124,18 @@
 #define ARMV8_MRC_DLR(Rt)      ARMV8_MRC_T1(15, 4, 3, 5, 1, Rt)
 #define ARMV8_MCR_DLR(Rt)      ARMV8_MCR_T1(15, 4, 3, 5, 1, Rt)
 
-#define ARMV8_DCPS1(IM)        (0xd4a00001 | (((IM) & 0xFFFF) << 5))
-#define ARMV8_DCPS2(IM)        (0xd4a00002 | (((IM) & 0xFFFF) << 5))
-#define ARMV8_DCPS3(IM)        (0xd4a00003 | (((IM) & 0xFFFF) << 5))
+#define ARMV8_DCPS1(IM)                (0xd4a00001 | (((IM) & 0xFFFF) << 5))
+#define ARMV8_DCPS2(IM)                (0xd4a00002 | (((IM) & 0xFFFF) << 5))
+#define ARMV8_DCPS3(IM)                (0xd4a00003 | (((IM) & 0xFFFF) << 5))
+#define ARMV8_DCPS(EL, IM)     (0xd4a00000 | (((IM) & 0xFFFF) << 5) | EL)
+#define ARMV8_DCPS_T1(EL)      (0xf78f8000 | EL)
+#define ARMV8_DRPS             0xd6bf03e0
+#define ARMV8_ERET_T1          0xf3de8f00
 
 #define ARMV8_DSB_SY                           0xd5033F9F
 #define ARMV8_DSB_SY_T1                                0xf3bf8f4f
+#define ARMV8_ISB                              0xd5033fdf
+#define ARMV8_ISB_SY_T1                                0xf3bf8f6f
 
 #define ARMV8_MRS(System, Rt)  (0xd5300000 | ((System) << 5) | (Rt))
 /* ARM V8 Move to system register. */
@@ -147,15 +152,42 @@
 
 #define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5))
 #define ARMV8_HLT(Im) (0x0D4400000 | ((Im & 0xffff) << 5))
+#define ARMV8_HLT_A1(Im) (0xE1000070 | ((Im & 0xFFF0) << 4) | (Im & 0xF))
+#define ARMV8_HLT_T1(Im) (0xba80 | (Im & 0x3f))
 
 #define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt))
 #define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F))
 #define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
 #define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
 
+#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd)
+#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd)
+#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd)
+
+#define ARMV8_LDRB_IP_T3(Rd, Rn) (0xf8100b01 | (Rn << 16) | (Rd << 12))
+#define ARMV8_LDRH_IP_T3(Rd, Rn) (0xf8300b02 | (Rn << 16) | (Rd << 12))
+#define ARMV8_LDRW_IP_T3(Rd, Rn) (0xf8500b04 | (Rn << 16) | (Rd << 12))
+
+#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd)
+#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
+#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
+
+#define ARMV8_STRB_IP_T3(Rd, Rn) (0xf8000b01 | (Rn << 16) | (Rd << 12))
+#define ARMV8_STRH_IP_T3(Rd, Rn) (0xf8200b02 | (Rn << 16) | (Rd << 12))
+#define ARMV8_STRW_IP_T3(Rd, Rn) (0xf8400b04 | (Rn << 16) | (Rd << 12))
+
+#define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd)
+#define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd)
+
+#define ARMV8_MRS_FPCR(Rt)     (0xd53b4400 | (Rt))
+#define ARMV8_MRS_FPSR(Rt)     (0xd53b4420 | (Rt))
+#define ARMV8_MSR_FPCR(Rt)     (0xd51b4400 | (Rt))
+#define ARMV8_MSR_FPSR(Rt)     (0xd51b4420 | (Rt))
+
 #define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
 
 enum armv8_opcode {
+       READ_REG_CTR,
        READ_REG_CLIDR,
        READ_REG_CSSELR,
        READ_REG_CCSIDR,
@@ -166,6 +198,19 @@ enum armv8_opcode {
        WRITE_REG_DSPSR,
        READ_REG_DSPSR,
        ARMV8_OPC_DSB_SY,
+       ARMV8_OPC_DCPS,
+       ARMV8_OPC_DRPS,
+       ARMV8_OPC_ISB_SY,
+       ARMV8_OPC_DCCISW,
+       ARMV8_OPC_DCCIVAC,
+       ARMV8_OPC_ICIVAU,
+       ARMV8_OPC_HLT,
+       ARMV8_OPC_STRB_IP,
+       ARMV8_OPC_STRH_IP,
+       ARMV8_OPC_STRW_IP,
+       ARMV8_OPC_LDRB_IP,
+       ARMV8_OPC_LDRH_IP,
+       ARMV8_OPC_LDRW_IP,
        ARMV8_OPC_NUM,
 };