target: Constify parameter of is_armv7m()

[fw/openocd] / src / target / armv8_dpm.h

diff --git a/src/target/armv8_dpm.h b/src/target/armv8_dpm.h
index 6470461e14650d8cb14de0b90e9a54dce0fd9606..c03935928b95ce6d9e492e8104b63c887e35d087 100644 (file)
--- a/src/target/armv8_dpm.h
+++ b/src/target/armv8_dpm.h
@@ -32,7 +32,7 @@ int armv8_dpm_setup(struct arm_dpm *dpm);
 int armv8_dpm_initialize(struct arm_dpm *dpm);
 
 int armv8_dpm_read_current_registers(struct arm_dpm *);
-int dpmv8_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
+int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
 
 
 int armv8_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
@@ -96,7 +96,7 @@ void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
 #define DRCR_RESTART                   (1 << 1)
 #define DRCR_CLEAR_EXCEPTIONS  (1 << 2)
 
-/* PRCR (processor debug status register) bits */
+/* PRSR (processor debug status register) bits */
 #define PRSR_PU                                        (1 << 0)
 #define PRSR_SPD                               (1 << 1)
 #define PRSR_RESET                             (1 << 2)
@@ -110,7 +110,13 @@ void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
 #define PRSR_SPMAD                             (1 << 10)
 #define PRSR_SDR                               (1 << 11)
 
+/* PRCR (processor debug control register) bits */
+#define PRCR_CORENPDRQ                 (1 << 0)
+#define PRCR_CWRR                              (1 << 2)
+#define PRCR_COREPURQ                  (1 << 3)
+
 void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
+void armv8_dpm_handle_exception(struct arm_dpm *dpm);
 enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm);
 
 #endif /* OPENOCD_TARGET_ARM_DPM_H */