openocd: src: replace the incomplete GPL-2.0-or-later license tag

[fw/openocd] / src / target / armv8_dpm.h

diff --git a/src/target/armv8_dpm.h b/src/target/armv8_dpm.h
index 416f4df02481946b0f41d0695ef7d159732e4050..19b33da6f06c7303375ca1f9b682600306a98984 100644 (file)
--- a/src/target/armv8_dpm.h
+++ b/src/target/armv8_dpm.h
@@ -1,21 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /*
  * Copyright (C) 2009 by David Brownell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef OPENOCD_TARGET_ARMV8_DPM_H
 #define OPENOCD_TARGET_ARMV8_DPM_H
 
 #include "arm_dpm.h"
+#include "helper/bits.h"
 
 /* forward-declare struct armv8_common */
 struct armv8_common;
@@ -31,13 +24,11 @@ struct armv8_common;
 int armv8_dpm_setup(struct arm_dpm *dpm);
 int armv8_dpm_initialize(struct arm_dpm *dpm);
 
-int armv8_dpm_read_current_registers(struct arm_dpm *);
-int dpmv8_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
-
+int armv8_dpm_read_current_registers(struct arm_dpm *dpm);
+int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
 
-int armv8_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
 
-void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
+int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
 
 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
  * Not all v7 bits are valid in v6.
@@ -96,7 +87,13 @@ void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
 #define DRCR_RESTART                   (1 << 1)
 #define DRCR_CLEAR_EXCEPTIONS  (1 << 2)
 
-/* PRCR (processor debug status register) bits */
+/* ECR (Execution Control Register) bits */
+#define ECR_RCE         BIT(1)
+
+/* ESR (Event Status Register) bits */
+#define ESR_RC          BIT(1)
+
+/* PRSR (processor debug status register) bits */
 #define PRSR_PU                                        (1 << 0)
 #define PRSR_SPD                               (1 << 1)
 #define PRSR_RESET                             (1 << 2)
@@ -110,6 +107,13 @@ void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
 #define PRSR_SPMAD                             (1 << 10)
 #define PRSR_SDR                               (1 << 11)
 
+/* PRCR (processor debug control register) bits */
+#define PRCR_CORENPDRQ                 (1 << 0)
+#define PRCR_CWRR                              (1 << 2)
+#define PRCR_COREPURQ                  (1 << 3)
+
 void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
+void armv8_dpm_handle_exception(struct arm_dpm *dpm, bool do_restore);
+enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm);
 
 #endif /* OPENOCD_TARGET_ARM_DPM_H */