target/arm_dap: check SWD DAP configuration

[fw/openocd] / src / target / armv8_cache.c

diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
index a641d04ab5f4f3fb9f30a091dd8a992f62806c02..f05ac07cd6dca2c6b705008138fc9097bcac02ce 100644 (file)
--- a/src/target/armv8_cache.c
+++ b/src/target/armv8_cache.c
@@ -194,7 +194,7 @@ static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
        int cl;
 
        if (armv8_cache->info == -1) {
-               command_print(cmd->ctx, "cache not yet identified");
+               command_print(cmd, "cache not yet identified");
                return ERROR_OK;
        }
 
@@ -202,11 +202,11 @@ static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
                struct armv8_arch_cache *arch = &(armv8_cache->arch[cl]);
 
                if (arch->ctype & 1) {
-                       command_print(cmd->ctx,
-                               "L%d I-Cache: linelen %" PRIi32
-                               ", associativity %" PRIi32
-                               ", nsets %" PRIi32
-                               ", cachesize %" PRId32 " KBytes",
+                       command_print(cmd,
+                               "L%d I-Cache: linelen %" PRIu32
+                               ", associativity %" PRIu32
+                               ", nsets %" PRIu32
+                               ", cachesize %" PRIu32 " KBytes",
                                cl+1,
                                arch->i_size.linelen,
                                arch->i_size.associativity,
@@ -215,11 +215,11 @@ static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
                }
 
                if (arch->ctype >= 2) {
-                       command_print(cmd->ctx,
-                               "L%d D-Cache: linelen %" PRIi32
-                               ", associativity %" PRIi32
-                               ", nsets %" PRIi32
-                               ", cachesize %" PRId32 " KBytes",
+                       command_print(cmd,
+                               "L%d D-Cache: linelen %" PRIu32
+                               ", associativity %" PRIu32
+                               ", nsets %" PRIu32
+                               ", cachesize %" PRIu32 " KBytes",
                                cl+1,
                                arch->d_u_size.linelen,
                                arch->d_u_size.associativity,
@@ -252,7 +252,7 @@ static int  armv8_flush_all_data(struct target *target)
                struct target_list *head;
                struct target *curr;
                head = target->head;
-               while (head != (struct target_list *)NULL) {
+               while (head) {
                        curr = head->target;
                        if (curr->state == TARGET_HALTED) {
                                LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
@@ -336,7 +336,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
 
        cache->iminline = 4UL << (ctr & 0xf);
        cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
-       LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
+       LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
                 ctr, cache->iminline, cache->dminline);
 
        /*  retrieve CLIDR */
@@ -373,13 +373,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
                                goto done;
                        cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
 
-                       LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
+                       LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
                                        cache->arch[cl].d_u_size.index,
                                        cache->arch[cl].d_u_size.index_shift,
                                        cache->arch[cl].d_u_size.way,
                                        cache->arch[cl].d_u_size.way_shift);
 
-                       LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+                       LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
                                        cache->arch[cl].d_u_size.linelen,
                                        cache->arch[cl].d_u_size.cachesize,
                                        cache->arch[cl].d_u_size.associativity);
@@ -393,13 +393,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
                                goto done;
                        cache->arch[cl].i_size = decode_cache_reg(cache_reg);
 
-                       LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
+                       LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
                                        cache->arch[cl].i_size.index,
                                        cache->arch[cl].i_size.index_shift,
                                        cache->arch[cl].i_size.way,
                                        cache->arch[cl].i_size.way_shift);
 
-                       LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+                       LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
                                        cache->arch[cl].i_size.linelen,
                                        cache->arch[cl].i_size.cachesize,
                                        cache->arch[cl].i_size.associativity);
@@ -417,7 +417,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
        armv8->armv8_mmu.armv8_cache.info = 1;
 
        /*  if no l2 cache initialize l1 data cache flush function function */
-       if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache == NULL) {
+       if (!armv8->armv8_mmu.armv8_cache.flush_all_data_cache) {
                armv8->armv8_mmu.armv8_cache.display_cache_info =
                        armv8_handle_inner_cache_info_command;
                armv8->armv8_mmu.armv8_cache.flush_all_data_cache =