target/armv7m: rework Cortex-M register handling part 1

[fw/openocd] / src / target / armv8.h

diff --git a/src/target/armv8.h b/src/target/armv8.h
index 02663cab2717977ba944bed7295b99b7aa863d5a..978b2ad4a1832eb6f024f2528413b5b270c5f165 100644 (file)
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -63,21 +63,62 @@ enum {
        ARMV8_PC = 32,
        ARMV8_xPSR = 33,
 
-       ARMV8_ELR_EL1 = 34,
-       ARMV8_ESR_EL1 = 35,
-       ARMV8_SPSR_EL1 = 36,
-
-       ARMV8_ELR_EL2 = 37,
-       ARMV8_ESR_EL2 = 38,
-       ARMV8_SPSR_EL2 = 39,
-
-       ARMV8_ELR_EL3 = 40,
-       ARMV8_ESR_EL3 = 41,
-       ARMV8_SPSR_EL3 = 42,
+       ARMV8_V0 = 34,
+       ARMV8_V1,
+       ARMV8_V2,
+       ARMV8_V3,
+       ARMV8_V4,
+       ARMV8_V5,
+       ARMV8_V6,
+       ARMV8_V7,
+       ARMV8_V8,
+       ARMV8_V9,
+       ARMV8_V10,
+       ARMV8_V11,
+       ARMV8_V12,
+       ARMV8_V13,
+       ARMV8_V14,
+       ARMV8_V15,
+       ARMV8_V16,
+       ARMV8_V17,
+       ARMV8_V18,
+       ARMV8_V19,
+       ARMV8_V20,
+       ARMV8_V21,
+       ARMV8_V22,
+       ARMV8_V23,
+       ARMV8_V24,
+       ARMV8_V25,
+       ARMV8_V26,
+       ARMV8_V27,
+       ARMV8_V28,
+       ARMV8_V29,
+       ARMV8_V30,
+       ARMV8_V31,
+       ARMV8_FPSR,
+       ARMV8_FPCR,
+
+       ARMV8_ELR_EL1 = 68,
+       ARMV8_ESR_EL1 = 69,
+       ARMV8_SPSR_EL1 = 70,
+
+       ARMV8_ELR_EL2 = 71,
+       ARMV8_ESR_EL2 = 72,
+       ARMV8_SPSR_EL2 = 73,
+
+       ARMV8_ELR_EL3 = 74,
+       ARMV8_ESR_EL3 = 75,
+       ARMV8_SPSR_EL3 = 76,
 
        ARMV8_LAST_REG,
 };
 
+enum run_control_op {
+       ARMV8_RUNCONTROL_UNKNOWN = 0,
+       ARMV8_RUNCONTROL_RESUME = 1,
+       ARMV8_RUNCONTROL_HALT = 2,
+       ARMV8_RUNCONTROL_STEP = 3,
+};
 
 #define ARMV8_COMMON_MAGIC 0x0A450AAA
 
@@ -98,7 +139,7 @@ struct armv8_l2x_cache {
 
 struct armv8_cachesize {
        uint32_t level_num;
-       /*  cache dimensionning */
+       /*  cache dimensioning */
        uint32_t linelen;
        uint32_t associativity;
        uint32_t nsets;
@@ -129,7 +170,7 @@ struct armv8_cache_common {
        /* l2 external unified cache if some */
        void *l2_cache;
        int (*flush_all_data_cache)(struct target *target);
-       int (*display_cache_info)(struct command_context *cmd_ctx,
+       int (*display_cache_info)(struct command_invocation *cmd,
                        struct armv8_cache_common *armv8_cache);
 };
 
@@ -175,10 +216,19 @@ struct armv8_common {
 
        struct arm_cti *cti;
 
+       /* last run-control command issued to this target (resume, halt, step) */
+       enum run_control_op last_run_control_op;
+
        /* Direct processor core register read and writes */
        int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
        int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
 
+       /* SIMD/FPU registers read/write interface */
+       int (*read_reg_u128)(struct armv8_common *armv8, int num,
+                       uint64_t *lvalue, uint64_t *hvalue);
+       int (*write_reg_u128)(struct armv8_common *armv8, int num,
+                       uint64_t lvalue, uint64_t hvalue);
+
        int (*examine_debug_reason)(struct target *target);
        int (*post_debug_entry)(struct target *target);
 
@@ -191,6 +241,11 @@ target_to_armv8(struct target *target)
        return container_of(target->arch_info, struct armv8_common, arm);
 }
 
+static inline bool is_armv8(struct armv8_common *armv8)
+{
+       return armv8->common_magic == ARMV8_COMMON_MAGIC;
+}
+
 /* register offsets from armv8.debug_base */
 #define CPUV8_DBG_MAINID0              0xD00
 #define CPUV8_DBG_CPUFEATURE0  0xD20
@@ -206,6 +261,7 @@ target_to_armv8(struct target *target)
 #define CPUV8_DBG_WFAR1                0x34
 #define CPUV8_DBG_DSCR         0x088
 #define CPUV8_DBG_DRCR         0x090
+#define CPUV8_DBG_ECCR         0x098
 #define CPUV8_DBG_PRCR         0x310
 #define CPUV8_DBG_PRSR         0x314
 
@@ -245,7 +301,7 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
                target_addr_t *val, int meminfo);
 int armv8_mmu_translate_va(struct target *target,  target_addr_t va, target_addr_t *val);
 
-int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv8_handle_cache_info_command(struct command_invocation *cmd,
                struct armv8_cache_common *armv8_cache);
 
 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
@@ -270,13 +326,16 @@ static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
                return 3;
        /* all Aarch64 modes */
        default:
-               return (core_mode >> 6) & 3;
+               return (core_mode >> 2) & 3;
        }
 }
 
+const char *armv8_mode_name(unsigned psr_mode);
 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
 
+extern void armv8_free_reg_cache(struct target *target);
+
 extern const struct command_registration armv8_command_handlers[];
 
 #endif /* OPENOCD_TARGET_ARMV8_H */