openocd: remove CamelCase symbols *xPSR*

[fw/openocd] / src / target / armv8.h

diff --git a/src/target/armv8.h b/src/target/armv8.h
index 6525d2601f803f05a0dce6f1f0cd52fafbfc2806..2ed3a65acd9e8fb3f015f99b690a71090d3a9d2a 100644 (file)
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -1,19 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *   Copyright (C) 2015 by David Ung                                       *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
  ***************************************************************************/
 
 #ifndef OPENOCD_TARGET_ARMV8_H
@@ -61,7 +49,7 @@ enum {
 
        ARMV8_SP = 31,
        ARMV8_PC = 32,
-       ARMV8_xPSR = 33,
+       ARMV8_XPSR = 33,
 
        ARMV8_V0 = 34,
        ARMV8_V1,
@@ -113,8 +101,14 @@ enum {
        ARMV8_LAST_REG,
 };
 
+enum run_control_op {
+       ARMV8_RUNCONTROL_UNKNOWN = 0,
+       ARMV8_RUNCONTROL_RESUME = 1,
+       ARMV8_RUNCONTROL_HALT = 2,
+       ARMV8_RUNCONTROL_STEP = 3,
+};
 
-#define ARMV8_COMMON_MAGIC 0x0A450AAA
+#define ARMV8_COMMON_MAGIC 0x0A450AAAU
 
 /* VA to PA translation operations opc2 values*/
 #define V2PCWPR  0
@@ -133,7 +127,7 @@ struct armv8_l2x_cache {
 
 struct armv8_cachesize {
        uint32_t level_num;
-       /*  cache dimensionning */
+       /*  cache dimensioning */
        uint32_t linelen;
        uint32_t associativity;
        uint32_t nsets;
@@ -164,7 +158,7 @@ struct armv8_cache_common {
        /* l2 external unified cache if some */
        void *l2_cache;
        int (*flush_all_data_cache)(struct target *target);
-       int (*display_cache_info)(struct command_context *cmd_ctx,
+       int (*display_cache_info)(struct command_invocation *cmd,
                        struct armv8_cache_common *armv8_cache);
 };
 
@@ -184,13 +178,14 @@ struct armv8_mmu_common {
 };
 
 struct armv8_common {
+       unsigned int common_magic;
+
        struct arm arm;
-       int common_magic;
        struct reg_cache *core_cache;
 
        /* Core Debug Unit */
        struct arm_dpm dpm;
-       uint32_t debug_base;
+       target_addr_t debug_base;
        struct adiv5_ap *debug_ap;
 
        const uint32_t *opcodes;
@@ -210,6 +205,9 @@ struct armv8_common {
 
        struct arm_cti *cti;
 
+       /* last run-control command issued to this target (resume, halt, step) */
+       enum run_control_op last_run_control_op;
+
        /* Direct processor core register read and writes */
        int (*read_reg_u64)(struct armv8_common *armv8, int num, uint64_t *value);
        int (*write_reg_u64)(struct armv8_common *armv8, int num, uint64_t value);
@@ -232,6 +230,11 @@ target_to_armv8(struct target *target)
        return container_of(target->arch_info, struct armv8_common, arm);
 }
 
+static inline bool is_armv8(struct armv8_common *armv8)
+{
+       return armv8->common_magic == ARMV8_COMMON_MAGIC;
+}
+
 /* register offsets from armv8.debug_base */
 #define CPUV8_DBG_MAINID0              0xD00
 #define CPUV8_DBG_CPUFEATURE0  0xD20
@@ -243,10 +246,11 @@ target_to_armv8(struct target *target)
 
 #define CPUV8_DBG_EDESR                0x20
 #define CPUV8_DBG_EDECR                0x24
-#define CPUV8_DBG_WFAR0                0x30
-#define CPUV8_DBG_WFAR1                0x34
+#define CPUV8_DBG_EDWAR0       0x30
+#define CPUV8_DBG_EDWAR1       0x34
 #define CPUV8_DBG_DSCR         0x088
 #define CPUV8_DBG_DRCR         0x090
+#define CPUV8_DBG_ECCR         0x098
 #define CPUV8_DBG_PRCR         0x310
 #define CPUV8_DBG_PRSR         0x314
 
@@ -286,7 +290,7 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
                target_addr_t *val, int meminfo);
 int armv8_mmu_translate_va(struct target *target,  target_addr_t va, target_addr_t *val);
 
-int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv8_handle_cache_info_command(struct command_invocation *cmd,
                struct armv8_cache_common *armv8_cache);
 
 void armv8_set_cpsr(struct arm *arm, uint32_t cpsr);
@@ -315,9 +319,12 @@ static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
        }
 }
 
+const char *armv8_mode_name(unsigned psr_mode);
 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
 
+extern void armv8_free_reg_cache(struct target *target);
+
 extern const struct command_registration armv8_command_handlers[];
 
 #endif /* OPENOCD_TARGET_ARMV8_H */