+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
/***************************************************************************
* Copyright (C) 2015 by David Ung *
* *
* Copyright (C) 2018 by Liviu Ionescu *
* <ilg@livius.net> *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
***************************************************************************/
#ifdef HAVE_CONFIG_H
.name = "HYP",
.psr = ARM_MODE_HYP,
},
+ {
+ .name = "UND",
+ .psr = ARM_MODE_UND,
+ },
{
.name = "SYS",
.psr = ARM_MODE_SYS,
break;
}
- if (retval == ERROR_OK && regval != NULL)
+ if (retval == ERROR_OK && regval)
*regval = value_64;
else
retval = ERROR_FAIL;
break;
}
- if (retval == ERROR_OK && regval != NULL)
+ if (retval == ERROR_OK && regval)
*regval = value;
return retval;
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
&value_r0);
+ if (retval != ERROR_OK)
+ return retval;
/* read r1 via dcc */
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
&value_r1);
- if (retval == ERROR_OK) {
- *lvalue = value_r1;
- *lvalue = ((*lvalue) << 32) | value_r0;
- } else
+ if (retval != ERROR_OK)
return retval;
+ *lvalue = value_r1;
+ *lvalue = ((*lvalue) << 32) | value_r0;
num++;
/* repeat above steps for high 64 bits of V register */
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
&value_r0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
&value_r1);
- if (retval == ERROR_OK) {
- *hvalue = value_r1;
- *hvalue = ((*hvalue) << 32) | value_r0;
- } else
+ if (retval != ERROR_OK)
return retval;
+ *hvalue = value_r1;
+ *hvalue = ((*hvalue) << 32) | value_r0;
break;
default:
retval = ERROR_FAIL;
retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
value_r1);
+ if (retval != ERROR_OK)
+ return retval;
/* write value_r0 to r0 via dcc then,
* move to double word register from r0:r1: "vmov vm, r0, r1"
*/
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
value_r0);
+ if (retval != ERROR_OK)
+ return retval;
num++;
/* repeat above steps for high 64 bits of V register */
retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
value_r1);
+ if (retval != ERROR_OK)
+ return retval;
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
value_r0);
if (n->name)
nsec = n->name;
- if (sec == NULL || nsec == NULL) {
+ if (!sec || !nsec) {
LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
return ERROR_FAIL;
}
return ERROR_OK;
}
- while (CMD_ARGC > argp) {
+ while (argp < CMD_ARGC) {
n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
if (!n->name) {
LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]);
reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
if (reg_list[i].reg_data_type) {
- if (armv8_regs[i].data_type == NULL)
+ if (!armv8_regs[i].data_type)
reg_list[i].reg_data_type->type = armv8_regs[i].type;
else
*reg_list[i].reg_data_type = *armv8_regs[i].data_type;