openocd: src/target: replace the GPL-2.0-or-later license tag

[fw/openocd] / src / target / armv8.c

diff --git a/src/target/armv8.c b/src/target/armv8.c
index 49e8b10b7b9994bc22ef246db0d8ebc70a8a38b5..f4ae1f55cf933479318812a650e0bd7e140757d1 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1,22 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *   Copyright (C) 2015 by David Ung                                       *
  *                                                                         *
  *   Copyright (C) 2018 by Liviu Ionescu                                   *
  *   <ilg@livius.net>                                                      *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H
@@ -77,6 +65,10 @@ static const struct {
                .name = "HYP",
                .psr = ARM_MODE_HYP,
        },
+       {
+               .name = "UND",
+               .psr = ARM_MODE_UND,
+       },
        {
                .name = "SYS",
                .psr = ARM_MODE_SYS,
@@ -204,7 +196,7 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
                break;
        }
 
-       if (retval == ERROR_OK && regval != NULL)
+       if (retval == ERROR_OK && regval)
                *regval = value_64;
        else
                retval = ERROR_FAIL;
@@ -430,7 +422,7 @@ static int armv8_read_reg32(struct armv8_common *armv8, int regnum, uint64_t *re
                break;
        }
 
-       if (retval == ERROR_OK && regval != NULL)
+       if (retval == ERROR_OK && regval)
                *regval = value;
 
        return retval;
@@ -454,29 +446,31 @@ static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum,
                retval = dpm->instr_read_data_r0(dpm,
                                ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
                                &value_r0);
+               if (retval != ERROR_OK)
+                       return retval;
                /* read r1 via dcc */
                retval = dpm->instr_read_data_dcc(dpm,
                                ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
                                &value_r1);
-               if (retval == ERROR_OK) {
-                       *lvalue = value_r1;
-                       *lvalue = ((*lvalue) << 32) | value_r0;
-               } else
+               if (retval != ERROR_OK)
                        return retval;
+               *lvalue = value_r1;
+               *lvalue = ((*lvalue) << 32) | value_r0;
 
                num++;
                /* repeat above steps for high 64 bits of V register */
                retval = dpm->instr_read_data_r0(dpm,
                                ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
                                &value_r0);
+               if (retval != ERROR_OK)
+                       return retval;
                retval = dpm->instr_read_data_dcc(dpm,
                                ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
                                &value_r1);
-               if (retval == ERROR_OK) {
-                       *hvalue = value_r1;
-                       *hvalue = ((*hvalue) << 32) | value_r0;
-               } else
+               if (retval != ERROR_OK)
                        return retval;
+               *hvalue = value_r1;
+               *hvalue = ((*hvalue) << 32) | value_r0;
                break;
        default:
                retval = ERROR_FAIL;
@@ -586,12 +580,16 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
                retval = dpm->instr_write_data_dcc(dpm,
                        ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
                        value_r1);
+               if (retval != ERROR_OK)
+                       return retval;
                /* write value_r0 to r0 via dcc then,
                 * move to double word register from r0:r1: "vmov vm, r0, r1"
                 */
                retval = dpm->instr_write_data_r0(dpm,
                        ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
                        value_r0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                num++;
                /* repeat above steps for high 64 bits of V register */
@@ -600,6 +598,8 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
                retval = dpm->instr_write_data_dcc(dpm,
                        ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
                        value_r1);
+               if (retval != ERROR_OK)
+                       return retval;
                retval = dpm->instr_write_data_r0(dpm,
                        ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
                        value_r0);
@@ -1046,14 +1046,14 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
                        return retval;
 
                n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f);
-               if (n->name != NULL)
+               if (n->name)
                        sec = n->name;
 
                n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0);
-               if (n->name != NULL)
+               if (n->name)
                        nsec = n->name;
 
-               if (sec == NULL || nsec == NULL) {
+               if (!sec || !nsec) {
                        LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
                        return ERROR_FAIL;
                }
@@ -1062,9 +1062,9 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
                return ERROR_OK;
        }
 
-       while (CMD_ARGC > argp) {
+       while (argp < CMD_ARGC) {
                n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
-               if (n->name == NULL) {
+               if (!n->name) {
                        LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]);
                        return ERROR_FAIL;
                }
@@ -1644,7 +1644,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
 
                reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
                if (reg_list[i].reg_data_type) {
-                       if (armv8_regs[i].data_type == NULL)
+                       if (!armv8_regs[i].data_type)
                                reg_list[i].reg_data_type->type = armv8_regs[i].type;
                        else
                                *reg_list[i].reg_data_type = *armv8_regs[i].data_type;
@@ -1730,7 +1730,7 @@ void armv8_free_reg_cache(struct target *target)
        struct reg_cache *cache = NULL, *cache32 = NULL;
 
        cache = arm->core_cache;
-       if (cache != NULL)
+       if (cache)
                cache32 = cache->next;
        armv8_free_cache(cache32, true);
        armv8_free_cache(cache, false);