+// SPDX-License-Identifier: GPL-2.0-or-later
+
/***************************************************************************
* Copyright (C) 2015 by David Ung *
* *
* Copyright (C) 2018 by Liviu Ionescu *
* <ilg@livius.net> *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
***************************************************************************/
#ifdef HAVE_CONFIG_H
.name = "HYP",
.psr = ARM_MODE_HYP,
},
+ {
+ .name = "UND",
+ .psr = ARM_MODE_UND,
+ },
{
.name = "SYS",
.psr = ARM_MODE_SYS,
retval = dpm->instr_read_data_r0_64(dpm,
ARMV8_MRS_DLR(0), &value_64);
break;
- case ARMV8_xPSR:
+ case ARMV8_XPSR:
retval = dpm->instr_read_data_r0(dpm,
ARMV8_MRS_DSPSR(0), &value);
value_64 = value;
break;
}
- if (retval == ERROR_OK && regval != NULL)
+ if (retval == ERROR_OK && regval)
*regval = value_64;
else
retval = ERROR_FAIL;
ARMV8_MSR_DLR(0),
value_64);
break;
- case ARMV8_xPSR:
+ case ARMV8_XPSR:
value = value_64;
retval = dpm->instr_write_data_r0(dpm,
ARMV8_MSR_DSPSR(0),
ARMV8_MRC_DLR(0),
&value);
break;
- case ARMV8_xPSR:
+ case ARMV8_XPSR:
retval = dpm->instr_read_data_r0(dpm,
ARMV8_MRC_DSPSR(0),
&value);
break;
case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS_xPSR_T1(1, 0),
+ ARMV8_MRS_XPSR_T1(1, 0),
&value);
break;
case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS_xPSR_T1(1, 0),
+ ARMV8_MRS_XPSR_T1(1, 0),
&value);
break;
case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS_xPSR_T1(1, 0),
+ ARMV8_MRS_XPSR_T1(1, 0),
&value);
break;
case ARMV8_FPSR:
break;
}
- if (retval == ERROR_OK && regval != NULL)
+ if (retval == ERROR_OK && regval)
*regval = value;
return retval;
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
&value_r0);
+ if (retval != ERROR_OK)
+ return retval;
/* read r1 via dcc */
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
&value_r1);
- if (retval == ERROR_OK) {
- *lvalue = value_r1;
- *lvalue = ((*lvalue) << 32) | value_r0;
- } else
+ if (retval != ERROR_OK)
return retval;
+ *lvalue = value_r1;
+ *lvalue = ((*lvalue) << 32) | value_r0;
num++;
/* repeat above steps for high 64 bits of V register */
retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
&value_r0);
+ if (retval != ERROR_OK)
+ return retval;
retval = dpm->instr_read_data_dcc(dpm,
ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
&value_r1);
- if (retval == ERROR_OK) {
- *hvalue = value_r1;
- *hvalue = ((*hvalue) << 32) | value_r0;
- } else
+ if (retval != ERROR_OK)
return retval;
+ *hvalue = value_r1;
+ *hvalue = ((*hvalue) << 32) | value_r0;
break;
default:
retval = ERROR_FAIL;
retval = dpm->instr_write_data_r0(dpm,
ARMV8_MCR_DLR(0), value);
break;
- case ARMV8_xPSR: /* CPSR */
+ case ARMV8_XPSR: /* CPSR */
/* read r0 from DCC, then "MCR r0, DSPSR" */
retval = dpm->instr_write_data_r0(dpm,
ARMV8_MCR_DSPSR(0), value);
break;
case ARMV8_SPSR_EL1: /* mapped to SPSR_svc */
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+ ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
value);
break;
case ARMV8_SPSR_EL2: /* mapped to SPSR_hyp */
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+ ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
value);
break;
case ARMV8_SPSR_EL3: /* mapped to SPSR_mon */
retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP_xPSR_T1(1, 0, 15),
+ ARMV8_MSR_GP_XPSR_T1(1, 0, 15),
value);
break;
case ARMV8_FPSR:
retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
value_r1);
+ if (retval != ERROR_OK)
+ return retval;
/* write value_r0 to r0 via dcc then,
* move to double word register from r0:r1: "vmov vm, r0, r1"
*/
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
value_r0);
+ if (retval != ERROR_OK)
+ return retval;
num++;
/* repeat above steps for high 64 bits of V register */
retval = dpm->instr_write_data_dcc(dpm,
ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
value_r1);
+ if (retval != ERROR_OK)
+ return retval;
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
value_r0);
if (retval != ERROR_OK)
return;
- /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
+ /* ARMV4_5_MRC(cpnum, op1, r0, crn, crm, op2) */
/* c5/c0 - {data, instruction} fault status registers */
retval = dpm->instr_read_data_r0(dpm,
unsigned int argp = 0;
int retval;
- static const Jim_Nvp nvp_ecatch_modes[] = {
+ static const struct jim_nvp nvp_ecatch_modes[] = {
{ .name = "off", .value = 0 },
{ .name = "nsec_el1", .value = (1 << 5) },
{ .name = "nsec_el2", .value = (2 << 5) },
{ .name = "sec_el13", .value = (5 << 1) },
{ .name = NULL, .value = -1 },
};
- const Jim_Nvp *n;
+ const struct jim_nvp *n;
if (CMD_ARGC == 0) {
const char *sec = NULL, *nsec = NULL;
if (retval != ERROR_OK)
return retval;
- n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f);
- if (n->name != NULL)
+ n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0x0f);
+ if (n->name)
sec = n->name;
- n = Jim_Nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0);
- if (n->name != NULL)
+ n = jim_nvp_value2name_simple(nvp_ecatch_modes, edeccr & 0xf0);
+ if (n->name)
nsec = n->name;
- if (sec == NULL || nsec == NULL) {
- LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02x", edeccr & 0xff);
+ if (!sec || !nsec) {
+ LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
return ERROR_FAIL;
}
return ERROR_OK;
}
- while (CMD_ARGC > argp) {
- n = Jim_Nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
- if (n->name == NULL) {
+ while (argp < CMD_ARGC) {
+ n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
+ if (!n->name) {
LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]);
return ERROR_FAIL;
}
static int armv8_setup_semihosting(struct target *target, int enable)
{
- struct arm *arm = target_to_arm(target);
-
- if (arm->core_state != ARM_STATE_AARCH64) {
- LOG_ERROR("semihosting only supported in AArch64 state\n");
- return ERROR_FAIL;
- }
-
return ERROR_OK;
}
return ERROR_OK;
}
-int armv8_aarch64_state(struct target *target)
+static int armv8_aarch64_state(struct target *target)
{
struct arm *arm = target_to_arm(target);
armv8_show_fault_registers(target);
if (target->debug_reason == DBG_REASON_WATCHPOINT)
- LOG_USER("Watchpoint triggered at PC %#08x",
- (unsigned) armv8->dpm.wp_pc);
+ LOG_USER("Watchpoint triggered at " TARGET_ADDR_FMT, armv8->dpm.wp_addr);
return ERROR_OK;
}
{ ARMV8_SP, "sp", 64, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
{ ARMV8_PC, "pc", 64, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.aarch64.core", NULL},
- { ARMV8_xPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED,
+ { ARMV8_XPSR, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED,
"general", "org.gnu.gdb.aarch64.core", aarch64_flags_cpsr},
{ ARMV8_V0, "v0", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
{ ARMV8_V1, "v1", 128, ARM_MODE_ANY, REG_TYPE_ARCH_DEFINED, "simdfp", "org.gnu.gdb.aarch64.fpu", aarch64v},
{ ARMV8_R13, 0, "sp", 32, ARM_MODE_ANY, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.core" },
{ ARMV8_R14, 0, "lr", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
{ ARMV8_PC, 0, "pc", 32, ARM_MODE_ANY, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.core" },
- { ARMV8_xPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
+ { ARMV8_XPSR, 0, "cpsr", 32, ARM_MODE_ANY, REG_TYPE_UINT32, "general", "org.gnu.gdb.arm.core" },
{ ARMV8_V0, 0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARMV8_V0, 8, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
{ ARMV8_V1, 0, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
if (reg_list[i].reg_data_type) {
- if (armv8_regs[i].data_type == NULL)
+ if (!armv8_regs[i].data_type)
reg_list[i].reg_data_type->type = armv8_regs[i].type;
else
*reg_list[i].reg_data_type = *armv8_regs[i].data_type;
LOG_ERROR("unable to allocate reg type list");
}
- arm->cpsr = reg_list + ARMV8_xPSR;
+ arm->cpsr = reg_list + ARMV8_XPSR;
arm->pc = reg_list + ARMV8_PC;
arm->core_cache = cache;
struct reg_cache *cache = NULL, *cache32 = NULL;
cache = arm->core_cache;
- if (cache != NULL)
+ if (cache)
cache32 = cache->next;
armv8_free_cache(cache32, true);
armv8_free_cache(cache, false);
/* Read register */
int retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + reg, &tmp);
- if (ERROR_OK != retval)
+ if (retval != ERROR_OK)
return retval;
/* clear bitfield */
projects / fw / openocd / blobdiff