target/armv7m: rework Cortex-M register handling part 1

[fw/openocd] / src / target / armv8.c

diff --git a/src/target/armv8.c b/src/target/armv8.c
index e271c1a9242c973fc2ae022740a3d13798aae39c..95efdc90bbd71e2220c3090feb800175019b1bbd 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -73,6 +73,10 @@ static const struct {
                .name = "ABT",
                .psr = ARM_MODE_ABT,
        },
+       {
+               .name = "HYP",
+               .psr = ARM_MODE_HYP,
+       },
        {
                .name = "SYS",
                .psr = ARM_MODE_SYS,
@@ -791,7 +795,7 @@ static uint8_t armv8_pa_size(uint32_t ps)
                        ret = 48;
                        break;
                default:
-                       LOG_INFO("Unknow physicall address size");
+                       LOG_INFO("Unknown physical address size");
                        break;
        }
        return ret;
@@ -818,7 +822,7 @@ static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target)
        armv8->armv8_mmu.ttbcr = ttbcr;
 
        /*
-        * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+        * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
         * document # ARM DDI 0406C
         */
        armv8->armv8_mmu.ttbr_range[0]  = 0xffffffff >> ttbcr_n;
@@ -848,7 +852,7 @@ static __attribute__((unused)) int armv8_read_ttbcr(struct target *target)
        if (retval != ERROR_OK)
                goto done;
 
-       /* claaer ttrr1_used and ttbr0_mask */
+       /* clear ttrr1_used and ttbr0_mask */
        memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
        memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
 
@@ -898,7 +902,7 @@ static __attribute__((unused)) int armv8_read_ttbcr(struct target *target)
                        goto done;
                break;
        default:
-               LOG_ERROR("unknow core state");
+               LOG_ERROR("unknown core state");
                retval = ERROR_FAIL;
                break;
        }
@@ -1050,11 +1054,11 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
                        nsec = n->name;
 
                if (sec == NULL || nsec == NULL) {
-                       LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02x", edeccr & 0xff);
+                       LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
                        return ERROR_FAIL;
                }
 
-               command_print(CMD_CTX, "Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec);
+               command_print(CMD, "Exception Catch: Secure: %s, Non-Secure: %s", sec, nsec);
                return ERROR_OK;
        }
 
@@ -1079,16 +1083,16 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
        return ERROR_OK;
 }
 
-int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv8_handle_cache_info_command(struct command_invocation *cmd,
        struct armv8_cache_common *armv8_cache)
 {
        if (armv8_cache->info == -1) {
-               command_print(cmd_ctx, "cache not yet identified");
+               command_print(cmd, "cache not yet identified");
                return ERROR_OK;
        }
 
        if (armv8_cache->display_cache_info)
-               armv8_cache->display_cache_info(cmd_ctx, armv8_cache);
+               armv8_cache->display_cache_info(cmd, armv8_cache);
        return ERROR_OK;
 }
 
@@ -1122,7 +1126,7 @@ int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
        return ERROR_OK;
 }
 
-int armv8_aarch64_state(struct target *target)
+static int armv8_aarch64_state(struct target *target)
 {
        struct arm *arm = target_to_arm(target);
 
@@ -1131,8 +1135,9 @@ int armv8_aarch64_state(struct target *target)
                return ERROR_FAIL;
        }
 
-       LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+       LOG_USER("%s halted in %s state due to %s, current mode: %s\n"
                "cpsr: 0x%8.8" PRIx32 " pc: 0x%" PRIx64 "%s",
+               target_name(target),
                armv8_state_strings[arm->core_state],
                debug_reason_name(target),
                armv8_mode_name(arm->core_mode),
@@ -1283,13 +1288,13 @@ static struct reg_data_type aarch64v[] = {
 };
 
 static struct reg_data_type_bitfield aarch64_cpsr_bits[] = {
-       {  0, 0 , REG_TYPE_UINT8 },
-       {  2, 3,  REG_TYPE_UINT8 },
-       {  4, 4 , REG_TYPE_UINT8 },
-       {  6, 6 , REG_TYPE_BOOL },
-       {  7, 7 , REG_TYPE_BOOL },
-       {  8, 8 , REG_TYPE_BOOL },
-       {  9, 9 , REG_TYPE_BOOL },
+       {  0,  0, REG_TYPE_UINT8 },
+       {  2,  3, REG_TYPE_UINT8 },
+       {  4,  4, REG_TYPE_UINT8 },
+       {  6,  6, REG_TYPE_BOOL },
+       {  7,  7, REG_TYPE_BOOL },
+       {  8,  8, REG_TYPE_BOOL },
+       {  9,  9, REG_TYPE_BOOL },
        { 20, 20, REG_TYPE_BOOL },
        { 21, 21, REG_TYPE_BOOL },
        { 28, 28, REG_TYPE_BOOL },
@@ -1302,16 +1307,16 @@ static struct reg_data_type_flags_field aarch64_cpsr_fields[] = {
        { "SP",  aarch64_cpsr_bits + 0,  aarch64_cpsr_fields + 1 },
        { "EL",  aarch64_cpsr_bits + 1,  aarch64_cpsr_fields + 2 },
        { "nRW", aarch64_cpsr_bits + 2,  aarch64_cpsr_fields + 3 },
-       { "F"  , aarch64_cpsr_bits + 3,  aarch64_cpsr_fields + 4 },
-       { "I"  , aarch64_cpsr_bits + 4,  aarch64_cpsr_fields + 5 },
-       { "A"  , aarch64_cpsr_bits + 5,  aarch64_cpsr_fields + 6 },
-       { "D"  , aarch64_cpsr_bits + 6,  aarch64_cpsr_fields + 7 },
-       { "IL" , aarch64_cpsr_bits + 7,  aarch64_cpsr_fields + 8 },
-       { "SS" , aarch64_cpsr_bits + 8,  aarch64_cpsr_fields + 9 },
-       { "V"  , aarch64_cpsr_bits + 9,  aarch64_cpsr_fields + 10 },
-       { "C"  , aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
-       { "Z"  , aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
-       { "N"  , aarch64_cpsr_bits + 12, NULL }
+       { "F",   aarch64_cpsr_bits + 3,  aarch64_cpsr_fields + 4 },
+       { "I",   aarch64_cpsr_bits + 4,  aarch64_cpsr_fields + 5 },
+       { "A",   aarch64_cpsr_bits + 5,  aarch64_cpsr_fields + 6 },
+       { "D",   aarch64_cpsr_bits + 6,  aarch64_cpsr_fields + 7 },
+       { "IL",  aarch64_cpsr_bits + 7,  aarch64_cpsr_fields + 8 },
+       { "SS",  aarch64_cpsr_bits + 8,  aarch64_cpsr_fields + 9 },
+       { "V",   aarch64_cpsr_bits + 9,  aarch64_cpsr_fields + 10 },
+       { "C",   aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
+       { "Z",   aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
+       { "N",   aarch64_cpsr_bits + 12, NULL }
 };
 
 static struct reg_data_type_flags aarch64_cpsr_flags[] = {
@@ -1753,7 +1758,8 @@ const struct command_registration armv8_command_handlers[] = {
 
 const char *armv8_get_gdb_arch(struct target *target)
 {
-       return "aarch64";
+       struct arm *arm = target_to_arm(target);
+       return arm->core_state == ARM_STATE_AARCH64 ? "aarch64" : "arm";
 }
 
 int armv8_get_gdb_reg_list(struct target *target,