target/cortex_m: faster reading of all CPU registers

[fw/openocd] / src / target / armv8.c

diff --git a/src/target/armv8.c b/src/target/armv8.c
index 43a365938a57b30b71fd16d1a6b9f91a180f0930..26116bb335c00655d2163a9ee94b8917b888f56d 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -454,29 +454,31 @@ static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum,
                retval = dpm->instr_read_data_r0(dpm,
                                ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
                                &value_r0);
+               if (retval != ERROR_OK)
+                       return retval;
                /* read r1 via dcc */
                retval = dpm->instr_read_data_dcc(dpm,
                                ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
                                &value_r1);
-               if (retval == ERROR_OK) {
-                       *lvalue = value_r1;
-                       *lvalue = ((*lvalue) << 32) | value_r0;
-               } else
+               if (retval != ERROR_OK)
                        return retval;
+               *lvalue = value_r1;
+               *lvalue = ((*lvalue) << 32) | value_r0;
 
                num++;
                /* repeat above steps for high 64 bits of V register */
                retval = dpm->instr_read_data_r0(dpm,
                                ARMV4_5_VMOV(1, 1, 0, (num >> 4), (num & 0xf)),
                                &value_r0);
+               if (retval != ERROR_OK)
+                       return retval;
                retval = dpm->instr_read_data_dcc(dpm,
                                ARMV4_5_MCR(14, 0, 1, 0, 5, 0),
                                &value_r1);
-               if (retval == ERROR_OK) {
-                       *hvalue = value_r1;
-                       *hvalue = ((*hvalue) << 32) | value_r0;
-               } else
+               if (retval != ERROR_OK)
                        return retval;
+               *hvalue = value_r1;
+               *hvalue = ((*hvalue) << 32) | value_r0;
                break;
        default:
                retval = ERROR_FAIL;
@@ -586,12 +588,16 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
                retval = dpm->instr_write_data_dcc(dpm,
                        ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
                        value_r1);
+               if (retval != ERROR_OK)
+                       return retval;
                /* write value_r0 to r0 via dcc then,
                 * move to double word register from r0:r1: "vmov vm, r0, r1"
                 */
                retval = dpm->instr_write_data_r0(dpm,
                        ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
                        value_r0);
+               if (retval != ERROR_OK)
+                       return retval;
 
                num++;
                /* repeat above steps for high 64 bits of V register */
@@ -600,6 +606,8 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
                retval = dpm->instr_write_data_dcc(dpm,
                        ARMV4_5_MRC(14, 0, 1, 0, 5, 0),
                        value_r1);
+               if (retval != ERROR_OK)
+                       return retval;
                retval = dpm->instr_write_data_r0(dpm,
                        ARMV4_5_VMOV(0, 1, 0, (num >> 4), (num & 0xf)),
                        value_r0);
@@ -1062,7 +1070,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
                return ERROR_OK;
        }
 
-       while (CMD_ARGC > argp) {
+       while (argp < CMD_ARGC) {
                n = jim_nvp_name2value_simple(nvp_ecatch_modes, CMD_ARGV[argp]);
                if (!n->name) {
                        LOG_ERROR("Unknown option: %s", CMD_ARGV[argp]);