target/stm8: add missing destroy_reg_param()

[fw/openocd] / src / target / armv8.c

diff --git a/src/target/armv8.c b/src/target/armv8.c
index 20f2b671c6da98af7271133fb4005646d9321830..1981e7c3d5765a39ee2140dfdda593400964c782 100644 (file)
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -936,6 +936,11 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
                        "Secure", "Not Secure"
        };
 
+       if (target->state != TARGET_HALTED) {
+               LOG_WARNING("target %s not halted", target_name(target));
+               return ERROR_TARGET_NOT_HALTED;
+       }
+
        retval = dpm->prepare(dpm);
        if (retval != ERROR_OK)
                return retval;
@@ -1017,11 +1022,24 @@ int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
        return ERROR_OK;
 }
 
+static int armv8_setup_semihosting(struct target *target, int enable)
+{
+       struct arm *arm = target_to_arm(target);
+
+       if (arm->core_state != ARM_STATE_AARCH64) {
+               LOG_ERROR("semihosting only supported in AArch64 state\n");
+               return ERROR_FAIL;
+       }
+
+       return ERROR_OK;
+}
+
 int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
 {
        struct arm *arm = &armv8->arm;
        arm->arch_info = armv8;
        target->arch_info = &armv8->arm;
+       arm->setup_semihosting = armv8_setup_semihosting;
        /*  target is useful in all function arm v4 5 compatible */
        armv8->arm.target = target;
        armv8->arm.common_magic = ARM_COMMON_MAGIC;
@@ -1050,7 +1068,7 @@ int armv8_aarch64_state(struct target *target)
                armv8_mode_name(arm->core_mode),
                buf_get_u32(arm->cpsr->value, 0, 32),
                buf_get_u64(arm->pc->value, 0, 64),
-               target->semihosting->is_active ? ", semihosting" : "");
+               (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "");
 
        return ERROR_OK;
 }
@@ -1459,6 +1477,9 @@ static int armv8_get_core_reg32(struct reg *reg)
        struct reg *reg64;
        int retval;
 
+       if (target->state != TARGET_HALTED)
+               return ERROR_TARGET_NOT_HALTED;
+
        /* get the corresponding Aarch64 register */
        reg64 = cache->reg_list + armv8_reg->num;
        if (reg64->valid) {
@@ -1482,6 +1503,9 @@ static int armv8_set_core_reg32(struct reg *reg, uint8_t *buf)
        struct reg *reg64 = cache->reg_list + armv8_reg->num;
        uint32_t value = buf_get_u32(buf, 0, 32);
 
+       if (target->state != TARGET_HALTED)
+               return ERROR_TARGET_NOT_HALTED;
+
        if (reg64 == arm->cpsr) {
                armv8_set_cpsr(arm, value);
        } else {
@@ -1650,6 +1674,11 @@ const struct command_registration armv8_command_handlers[] = {
        COMMAND_REGISTRATION_DONE
 };
 
+const char *armv8_get_gdb_arch(struct target *target)
+{
+       return "aarch64";
+}
+
 int armv8_get_gdb_reg_list(struct target *target,
        struct reg **reg_list[], int *reg_list_size,
        enum target_register_class reg_class)