* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
-#ifndef ARMV7M_COMMON_H
-#define ARMV7M_COMMON_H
+#ifndef OPENOCD_TARGET_ARMV7M_H
+#define OPENOCD_TARGET_ARMV7M_H
#include "arm_adi_v5.h"
#include "arm.h"
+#include "armv7m_trace.h"
-/* define for enabling armv7 gdb workarounds */
-#if 1
-#define ARMV7_GDB_HACKS
-#endif
-
-#ifdef ARMV7_GDB_HACKS
-extern uint8_t armv7m_gdb_dummy_cpsr_value[];
-extern struct reg armv7m_gdb_dummy_cpsr_reg;
-#endif
-
-enum armv7m_mode {
- ARMV7M_MODE_THREAD = 0,
- ARMV7M_MODE_USER_THREAD = 1,
- ARMV7M_MODE_HANDLER = 2,
- ARMV7M_MODE_ANY = -1
-};
-
-extern char *armv7m_mode_strings[];
extern const int armv7m_psp_reg_map[];
extern const int armv7m_msp_reg_map[];
-enum armv7m_regtype {
- ARMV7M_REGISTER_CORE_GP,
- ARMV7M_REGISTER_CORE_SP,
- ARMV7M_REGISTER_MEMMAP
-};
+const char *armv7m_exception_string(int number);
+
+/* Cortex-M DCRSR.REGSEL selectors */
+enum {
+ ARMV7M_REGSEL_R0,
+ ARMV7M_REGSEL_R1,
+ ARMV7M_REGSEL_R2,
+ ARMV7M_REGSEL_R3,
+
+ ARMV7M_REGSEL_R4,
+ ARMV7M_REGSEL_R5,
+ ARMV7M_REGSEL_R6,
+ ARMV7M_REGSEL_R7,
-char *armv7m_exception_string(int number);
+ ARMV7M_REGSEL_R8,
+ ARMV7M_REGSEL_R9,
+ ARMV7M_REGSEL_R10,
+ ARMV7M_REGSEL_R11,
+
+ ARMV7M_REGSEL_R12,
+ ARMV7M_REGSEL_R13,
+ ARMV7M_REGSEL_R14,
+ ARMV7M_REGSEL_PC = 15,
+
+ ARMV7M_REGSEL_xPSR = 16,
+ ARMV7M_REGSEL_MSP,
+ ARMV7M_REGSEL_PSP,
+
+ ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL = 0x14,
+ ARMV7M_REGSEL_FPSCR = 0x21,
+
+ /* 32bit Floating-point registers */
+ ARMV7M_REGSEL_S0 = 0x40,
+ ARMV7M_REGSEL_S1,
+ ARMV7M_REGSEL_S2,
+ ARMV7M_REGSEL_S3,
+ ARMV7M_REGSEL_S4,
+ ARMV7M_REGSEL_S5,
+ ARMV7M_REGSEL_S6,
+ ARMV7M_REGSEL_S7,
+ ARMV7M_REGSEL_S8,
+ ARMV7M_REGSEL_S9,
+ ARMV7M_REGSEL_S10,
+ ARMV7M_REGSEL_S11,
+ ARMV7M_REGSEL_S12,
+ ARMV7M_REGSEL_S13,
+ ARMV7M_REGSEL_S14,
+ ARMV7M_REGSEL_S15,
+ ARMV7M_REGSEL_S16,
+ ARMV7M_REGSEL_S17,
+ ARMV7M_REGSEL_S18,
+ ARMV7M_REGSEL_S19,
+ ARMV7M_REGSEL_S20,
+ ARMV7M_REGSEL_S21,
+ ARMV7M_REGSEL_S22,
+ ARMV7M_REGSEL_S23,
+ ARMV7M_REGSEL_S24,
+ ARMV7M_REGSEL_S25,
+ ARMV7M_REGSEL_S26,
+ ARMV7M_REGSEL_S27,
+ ARMV7M_REGSEL_S28,
+ ARMV7M_REGSEL_S29,
+ ARMV7M_REGSEL_S30,
+ ARMV7M_REGSEL_S31,
+};
/* offsets into armv7m core register cache */
enum {
/* for convenience, the first set of indices match
- * the Cortex-M3/-M4 DCRSR selectors
+ * the Cortex-M DCRSR.REGSEL selectors
*/
- ARMV7M_R0,
- ARMV7M_R1,
- ARMV7M_R2,
- ARMV7M_R3,
-
- ARMV7M_R4,
- ARMV7M_R5,
- ARMV7M_R6,
- ARMV7M_R7,
-
- ARMV7M_R8,
- ARMV7M_R9,
- ARMV7M_R10,
- ARMV7M_R11,
-
- ARMV7M_R12,
- ARMV7M_R13,
- ARMV7M_R14,
- ARMV7M_PC = 15,
-
- ARMV7M_xPSR = 16,
- ARMV7M_MSP,
- ARMV7M_PSP,
-
- /* this next set of indices is arbitrary */
+ ARMV7M_R0 = ARMV7M_REGSEL_R0,
+ ARMV7M_R1 = ARMV7M_REGSEL_R1,
+ ARMV7M_R2 = ARMV7M_REGSEL_R2,
+ ARMV7M_R3 = ARMV7M_REGSEL_R3,
+
+ ARMV7M_R4 = ARMV7M_REGSEL_R4,
+ ARMV7M_R5 = ARMV7M_REGSEL_R5,
+ ARMV7M_R6 = ARMV7M_REGSEL_R6,
+ ARMV7M_R7 = ARMV7M_REGSEL_R7,
+
+ ARMV7M_R8 = ARMV7M_REGSEL_R8,
+ ARMV7M_R9 = ARMV7M_REGSEL_R9,
+ ARMV7M_R10 = ARMV7M_REGSEL_R10,
+ ARMV7M_R11 = ARMV7M_REGSEL_R11,
+
+ ARMV7M_R12 = ARMV7M_REGSEL_R12,
+ ARMV7M_R13 = ARMV7M_REGSEL_R13,
+ ARMV7M_R14 = ARMV7M_REGSEL_R14,
+ ARMV7M_PC = ARMV7M_REGSEL_PC,
+
+ ARMV7M_xPSR = ARMV7M_REGSEL_xPSR,
+ ARMV7M_MSP = ARMV7M_REGSEL_MSP,
+ ARMV7M_PSP = ARMV7M_REGSEL_PSP,
+
+ /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
ARMV7M_PRIMASK,
ARMV7M_BASEPRI,
ARMV7M_FAULTMASK,
ARMV7M_CONTROL,
- /* 32bit Floating-point registers */
- ARMV7M_S0,
- ARMV7M_S1,
- ARMV7M_S2,
- ARMV7M_S3,
- ARMV7M_S4,
- ARMV7M_S5,
- ARMV7M_S6,
- ARMV7M_S7,
- ARMV7M_S8,
- ARMV7M_S9,
- ARMV7M_S10,
- ARMV7M_S11,
- ARMV7M_S12,
- ARMV7M_S13,
- ARMV7M_S14,
- ARMV7M_S15,
- ARMV7M_S16,
- ARMV7M_S17,
- ARMV7M_S18,
- ARMV7M_S19,
- ARMV7M_S20,
- ARMV7M_S21,
- ARMV7M_S22,
- ARMV7M_S23,
- ARMV7M_S24,
- ARMV7M_S25,
- ARMV7M_S26,
- ARMV7M_S27,
- ARMV7M_S28,
- ARMV7M_S29,
- ARMV7M_S30,
- ARMV7M_S31,
-
/* 64bit Floating-point registers */
ARMV7M_D0,
ARMV7M_D1,
ARMV7M_D14,
ARMV7M_D15,
- /* Floating-point status registers */
- ARMV7M_FPSID,
+ /* Floating-point status register */
ARMV7M_FPSCR,
- ARMV7M_FPEXC,
ARMV7M_LAST_REG,
};
enum {
FP_NONE = 0,
FPv4_SP,
+ FPv5_SP,
+ FPv5_DP,
};
+#define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1)
+#define ARMV7M_NUM_CORE_REGS_NOFP (ARMV7M_CONTROL + 1)
+
#define ARMV7M_COMMON_MAGIC 0x2A452A45
struct armv7m_common {
struct arm arm;
int common_magic;
- struct reg_cache *core_cache;
- enum armv7m_mode core_mode;
int exception_number;
- struct adiv5_dap dap;
- int fp_feature;
+ /* AP this processor is connected to in the DAP */
+ struct adiv5_ap *debug_ap;
+ int fp_feature;
uint32_t demcr;
- /* Direct processor core register read and writes */
- int (*load_core_reg_u32)(struct target *target,
- enum armv7m_regtype type, uint32_t num, uint32_t *value);
- int (*store_core_reg_u32)(struct target *target,
- enum armv7m_regtype type, uint32_t num, uint32_t value);
+ /* stlink is a high level adapter, does not support all functions */
+ bool stlink;
- /* register cache to processor synchronization */
- int (*read_core_reg)(struct target *target, unsigned num);
- int (*write_core_reg)(struct target *target, unsigned num);
+ struct armv7m_trace_config trace_config;
+
+ /* Direct processor core register read and writes */
+ int (*load_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t *value);
+ int (*store_core_reg_u32)(struct target *target, uint32_t regsel, uint32_t value);
int (*examine_debug_reason)(struct target *target);
int (*post_debug_entry)(struct target *target);
return container_of(target->arch_info, struct armv7m_common, arm);
}
-static inline bool is_armv7m(struct armv7m_common *armv7m)
+static inline bool is_armv7m(const struct armv7m_common *armv7m)
{
return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
}
struct armv7m_algorithm {
int common_magic;
- enum armv7m_mode core_mode;
+ enum arm_mode core_mode;
uint32_t context[ARMV7M_LAST_REG]; /* ARMV7M_NUM_REGS */
};
-struct armv7m_core_reg {
- uint32_t num;
- enum armv7m_regtype type;
- struct target *target;
- struct armv7m_common *armv7m_common;
-};
-
struct reg_cache *armv7m_build_reg_cache(struct target *target);
+void armv7m_free_reg_cache(struct target *target);
+
enum armv7m_mode armv7m_number_to_mode(int number);
int armv7m_mode_to_number(enum armv7m_mode mode);
int armv7m_arch_state(struct target *target);
int armv7m_get_gdb_reg_list(struct target *target,
- struct reg **reg_list[], int *reg_list_size);
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class);
int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m);
int armv7m_run_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
int timeout_ms, void *arch_info);
int armv7m_start_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t entry_point, uint32_t exit_point,
+ target_addr_t entry_point, target_addr_t exit_point,
void *arch_info);
int armv7m_wait_algorithm(struct target *target,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
- uint32_t exit_point, int timeout_ms,
+ target_addr_t exit_point, int timeout_ms,
void *arch_info);
int armv7m_invalidate_core_regs(struct target *target);
int armv7m_restore_context(struct target *target);
int armv7m_checksum_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *checksum);
+ target_addr_t address, uint32_t count, uint32_t *checksum);
int armv7m_blank_check_memory(struct target *target,
- uint32_t address, uint32_t count, uint32_t *blank);
+ struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found);
extern const struct command_registration armv7m_command_handlers[];
-#endif /* ARMV7M_H */
+#endif /* OPENOCD_TARGET_ARMV7M_H */
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