telnet: auto-completion of "registered" commands

[fw/openocd] / src / target / armv7m.h

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index bd10905b84f6e95fd8f92a858d69794a91b7451a..652dbe798e5112b79a9e174c798a4be882071416 100644 (file)
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -128,6 +128,16 @@ enum {
        ARMV7M_PSP = ARMV7M_REGSEL_PSP,
 
        /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
+
+       /* working register for packing/unpacking special regs, hidden from gdb */
+       ARMV7M_PMSK_BPRI_FLTMSK_CTRL,
+
+       /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
+        * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
+        * cache only and are not flushed to CPU HW register.
+        * To trigger write to CPU HW register, add
+        *              armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
+        */
        ARMV7M_PRIMASK,
        ARMV7M_BASEPRI,
        ARMV7M_FAULTMASK,
@@ -154,18 +164,22 @@ enum {
        /* Floating-point status register */
        ARMV7M_FPSCR,
 
+       /* for convenience add registers' block delimiters */
        ARMV7M_LAST_REG,
+       ARMV7M_CORE_FIRST_REG = ARMV7M_R0,
+       ARMV7M_CORE_LAST_REG = ARMV7M_xPSR,
+       ARMV7M_FPU_FIRST_REG = ARMV7M_D0,
+       ARMV7M_FPU_LAST_REG = ARMV7M_FPSCR,
 };
 
 enum {
        FP_NONE = 0,
-       FPv4_SP,
-       FPv5_SP,
-       FPv5_DP,
+       FPV4_SP,
+       FPV5_SP,
+       FPV5_DP,
 };
 
-#define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1)
-#define ARMV7M_NUM_CORE_REGS_NOFP (ARMV7M_CONTROL + 1)
+#define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
 
 #define ARMV7M_COMMON_MAGIC 0x2A452A45