mips32: Sync Caches to Make Instr Writes Effective

[fw/openocd] / src / target / armv7m.c

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index bd5aa147afc2f5560d579df5f874d0dab02683ed..fff5dd84062d1c8b7850f5f525f443dd82a577f8 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -82,7 +82,7 @@ struct reg armv7m_gdb_dummy_cpsr_reg =
  */
 static const struct {
        unsigned id;
-       char *name;
+       const char *name;
        unsigned bits;
 } armv7m_regs[] = {
        { ARMV7M_R0, "r0", 32 },
@@ -313,9 +313,9 @@ static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int
        }
 
        armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
-       if (pc != exit_point)
+       if (exit_point && (pc != exit_point))
        {
-               LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+               LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
                return ERROR_TARGET_TIMEOUT;
        }
 
@@ -562,6 +562,8 @@ int armv7m_checksum_memory(struct target *target,
        struct reg_param reg_params[2];
        int retval;
 
+       /* see contib/loaders/checksum/armv7m_crc.s for src */
+
        static const uint16_t cortex_m3_crc_code[] = {
                0x4602,                                 /* mov  r2, r0 */
                0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */