mips: mips32_pracc_exec error propagation fixes

[fw/openocd] / src / target / armv7m.c

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 1216a45fbe2564e3af9f5dd16dce8d43566e53d3..fff5dd84062d1c8b7850f5f525f443dd82a577f8 100644 (file)
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -82,7 +82,7 @@ struct reg armv7m_gdb_dummy_cpsr_reg =
  */
 static const struct {
        unsigned id;
-       char *name;
+       const char *name;
        unsigned bits;
 } armv7m_regs[] = {
        { ARMV7M_R0, "r0", 32 },
@@ -139,9 +139,6 @@ int armv7m_restore_context(struct target *target)
                }
        }
 
-       if (armv7m->post_restore_context)
-               armv7m->post_restore_context(target);
-
        return ERROR_OK;
 }
 
@@ -316,9 +313,9 @@ static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int
        }
 
        armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
-       if (pc != exit_point)
+       if (exit_point && (pc != exit_point))
        {
-               LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+               LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
                return ERROR_TARGET_TIMEOUT;
        }
 
@@ -530,7 +527,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
        return cache;
 }
 
-int armv7m_setup_semihosting(struct target *target, int enable)
+static int armv7m_setup_semihosting(struct target *target, int enable)
 {
        /* nothing todo for armv7m */
        return ERROR_OK;
@@ -565,6 +562,8 @@ int armv7m_checksum_memory(struct target *target,
        struct reg_param reg_params[2];
        int retval;
 
+       /* see contib/loaders/checksum/armv7m_crc.s for src */
+
        static const uint16_t cortex_m3_crc_code[] = {
                0x4602,                                 /* mov  r2, r0 */
                0xF04F, 0x30FF,                 /* mov  r0, #0xffffffff */
@@ -618,8 +617,10 @@ int armv7m_checksum_memory(struct target *target,
        buf_set_u32(reg_params[0].value, 0, 32, address);
        buf_set_u32(reg_params[1].value, 0, 32, count);
 
+       int timeout = 20000 * (1 + (count / (1024 * 1024)));
+
        if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
-               crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
+               crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), timeout, &armv7m_info)) != ERROR_OK)
        {
                LOG_ERROR("error executing cortex_m3 crc algorithm");
                destroy_reg_param(&reg_params[0]);