* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2007,2008 Øyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
#include "config.h"
#endif
-#include "replacements.h"
-
#include "armv7m.h"
-#include "register.h"
-#include "target.h"
-#include "log.h"
-#include "jtag.h"
-#include "arm_jtag.h"
-#include <stdlib.h>
-#include <string.h>
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
char* armv7m_mode_strings[] =
{
- "Handler", "Thread"
-};
-
-char* armv7m_state_strings[] =
-{
- "Thumb", "Debug"
+ "Thread", "Thread (User)", "Handler",
};
char* armv7m_exception_strings[] =
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
"sp", "lr", "pc",
"xPSR", "msp", "psp",
- /* Registers accessed through MSR instructions */
- /* "apsr", "iapsr", "ipsr", "epsr", */
+ /* Registers accessed through special reg 20 */
"primask", "basepri", "faultmask", "control"
};
-char* armv7m_core_dbgreg_list[] =
+uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+reg_t armv7m_gdb_dummy_fp_reg =
{
- /* Registers accessed through core debug */
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
- "sp", "lr", "pc",
- "xPSR", "msp", "psp",
- /* Registers accessed through MSR instructions */
- /* "dbg_apsr", "iapsr", "ipsr", "epsr", */
- "primask", "basepri", "faultmask", "dbg_control"
+ "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
-u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
-reg_t armv7m_gdb_dummy_fp_reg =
+reg_t armv7m_gdb_dummy_fps_reg =
{
- "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
+ "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
-armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
+#ifdef ARMV7_GDB_HACKS
+uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
+
+reg_t armv7m_gdb_dummy_cpsr_reg =
+{
+ "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
+};
+#endif
+
+armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
{
/* CORE_GP are accesible using the core debug registers */
{0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
{11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
{12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
{13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
+ {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
{15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
{16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
{17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
{18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
- /* CORE_SP are accesible using MSR and MRS instructions */
-#if 0
- {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
- {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
- {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
- {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
-#endif
-
- {0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
- {0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
- {0x13, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
- {0x14, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
+ /* CORE_SP are accesible using coreregister 20 */
+ {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
+ {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
+ {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
+ {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
};
int armv7m_core_reg_arch_type = -1;
-
-/* Keep different contexts for the process being debugged and debug algorithms */
-enum armv7m_runcontext armv7m_get_context(target_t *target)
-{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
- if (armv7m->process_context == armv7m->core_cache)
- return ARMV7M_PROCESS_CONTEXT;
- if (armv7m->debug_context == armv7m->core_cache)
- return ARMV7M_DEBUG_CONTEXT;
-
- ERROR("Invalid runcontext");
- exit(-1);
-}
-
-int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
-{
- int i;
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
- if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET))
- {
- WARNING("target not halted, switch context ");
- return ERROR_TARGET_NOT_HALTED;
- }
-
- if (new_ctx == armv7m_get_context(target))
- return ERROR_OK;
-
- switch (new_ctx)
- {
- case ARMV7M_PROCESS_CONTEXT:
- armv7m->core_cache = armv7m->process_context;
- break;
- case ARMV7M_DEBUG_CONTEXT:
- armv7m->core_cache = armv7m->debug_context;
- break;
- default:
- ERROR("Invalid runcontext");
- exit(-1);
- }
- /* Mark registers in new context as dirty to force reload when run */
-
- for (i = 0; i < armv7m->core_cache->num_regs; i++)
- {
- armv7m->core_cache->reg_list[i].dirty = 1;
- }
-
- return ERROR_OK;
-}
+int armv7m_dummy_core_reg_arch_type = -1;
int armv7m_restore_context(target_t *target)
{
int i;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- DEBUG(" ");
+ LOG_DEBUG(" ");
if (armv7m->pre_restore_context)
armv7m->pre_restore_context(target);
-
+
for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
{
if (armv7m->core_cache->reg_list[i].dirty)
armv7m->write_core_reg(target, i);
}
}
-
+
if (armv7m->post_restore_context)
armv7m->post_restore_context(target);
-
- return ERROR_OK;
+
+ return ERROR_OK;
}
/* Core state functions */
char *armv7m_exception_string(int number)
{
static char enamebuf[32];
-
+
if ((number < 0) | (number > 511))
return "Invalid exception";
if (number < 16)
armv7m_core_reg_t *armv7m_reg = reg->arch_info;
target_t *target = armv7m_reg->target;
armv7m_common_t *armv7m_target = target->arch_info;
-
+
if (target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
}
retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
-
+
return retval;
}
-int armv7m_set_core_reg(reg_t *reg, u8 *buf)
+int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
{
armv7m_core_reg_t *armv7m_reg = reg->arch_info;
target_t *target = armv7m_reg->target;
- u32 value = buf_get_u32(buf, 0, 32);
-
+ uint32_t value = buf_get_u32(buf, 0, 32);
+
if (target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
}
-
+
buf_set_u32(reg->value, 0, 32, value);
reg->dirty = 1;
reg->valid = 1;
int armv7m_read_core_reg(struct target_s *target, int num)
{
- u32 reg_value;
+ uint32_t reg_value;
int retval;
armv7m_core_reg_t * armv7m_core_reg;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
-
+
if ((num < 0) || (num >= ARMV7NUMCOREREGS))
return ERROR_INVALID_ARGUMENTS;
buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
armv7m->core_cache->reg_list[num].valid = 1;
armv7m->core_cache->reg_list[num].dirty = 0;
-
- return ERROR_OK;
+
+ return retval;
}
int armv7m_write_core_reg(struct target_s *target, int num)
{
int retval;
- u32 reg_value;
+ uint32_t reg_value;
armv7m_core_reg_t *armv7m_core_reg;
-
+
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
if ((num < 0) || (num >= ARMV7NUMCOREREGS))
return ERROR_INVALID_ARGUMENTS;
-
+
reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
if (retval != ERROR_OK)
{
- ERROR("JTAG failure");
+ LOG_ERROR("JTAG failure");
armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
return ERROR_JTAG_DEVICE_ERROR;
}
- DEBUG("write core reg %i value 0x%x", num , reg_value);
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
armv7m->core_cache->reg_list[num].valid = 1;
armv7m->core_cache->reg_list[num].dirty = 0;
-
+
return ERROR_OK;
}
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
int i;
-
+
for (i = 0; i < armv7m->core_cache->num_regs; i++)
{
armv7m->core_cache->reg_list[i].valid = 0;
armv7m->core_cache->reg_list[i].dirty = 0;
}
-
+
return ERROR_OK;
}
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
int i;
-
+
*reg_list_size = 26;
*reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
-
- /* TODOLATER correct list of registers, names ? */
- for (i = 0; i < *reg_list_size; i++)
+
+ for (i = 0; i < 16; i++)
+ {
+ (*reg_list)[i] = &armv7m->core_cache->reg_list[i];
+ }
+
+ for (i = 16; i < 24; i++)
+ {
+ (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
+ }
+
+ (*reg_list)[24] = &armv7m_gdb_dummy_fps_reg;
+
+#ifdef ARMV7_GDB_HACKS
+ /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
+ (*reg_list)[25] = &armv7m_gdb_dummy_cpsr_reg;
+
+ /* ARMV7M is always in thumb mode, try to make GDB understand this
+ * if it does not support this arch */
+ *((char*)armv7m->core_cache->reg_list[15].value) |= 1;
+#else
+ (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
+#endif
+
+ return ERROR_OK;
+}
+
+/* run to exit point. return error if exit point was not reached. */
+static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, armv7m_common_t *armv7m)
+{
+ uint32_t pc;
+ int retval;
+ /* This code relies on the target specific resume() and poll()->debug_entry()
+ * sequence to write register values to the processor and the read them back */
+ if ((retval = target_resume(target, 0, entry_point, 1, 1)) != ERROR_OK)
+ {
+ return retval;
+ }
+
+ retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
+ /* If the target fails to halt due to the breakpoint, force a halt */
+ if (retval != ERROR_OK || target->state != TARGET_HALTED)
+ {
+ if ((retval=target_halt(target))!=ERROR_OK)
+ return retval;
+ if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
+ {
+ return retval;
+ }
+ return ERROR_TARGET_TIMEOUT;
+ }
+
+ armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
+ if (pc != exit_point)
{
- if (i < ARMV7NUMCOREREGS)
- (*reg_list)[i] = &armv7m->process_context->reg_list[i];
- else
- (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
+ LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+ return ERROR_TARGET_TIMEOUT;
}
- /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
- armv7m->process_context->reg_list[15].value[0] |= 1;
- (*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
+
return ERROR_OK;
}
-int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
+int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
+ enum armv7m_mode core_mode = armv7m->core_mode;
int retval = ERROR_OK;
- u32 pc;
int i;
+ uint32_t context[ARMV7NUMCOREREGS];
if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
{
- ERROR("current target isn't an ARMV7M target");
+ LOG_ERROR("current target isn't an ARMV7M target");
return ERROR_TARGET_INVALID;
}
-
+
if (target->state != TARGET_HALTED)
{
- WARNING("target not halted");
+ LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
+
/* refresh core register cache */
- /* Not needed if core register cache is always consistent with target process state */
- armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
-
+ /* Not needed if core register cache is always consistent with target process state */
+ for (i = 0; i < ARMV7NUMCOREREGS; i++)
+ {
+ if (!armv7m->core_cache->reg_list[i].valid)
+ armv7m->read_core_reg(target, i);
+ context[i] = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
+ }
+
for (i = 0; i < num_mem_params; i++)
{
- target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+ if ((retval=target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value))!=ERROR_OK)
+ return retval;
}
-
+
for (i = 0; i < num_reg_params; i++)
{
reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
- u32 regvalue;
-
+// uint32_t regvalue;
+
if (!reg)
{
- ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+ LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
exit(-1);
}
-
+
if (reg->size != reg_params[i].size)
{
- ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
+ LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
exit(-1);
}
-
- regvalue = buf_get_u32(reg_params[i].value, 0, 32);
+
+// regvalue = buf_get_u32(reg_params[i].value, 0, 32);
armv7m_set_core_reg(reg, reg_params[i].value);
}
-
+
+ if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
+ {
+ LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
+ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
+ armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
+ armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
+ }
+
/* ARMV7M always runs in Thumb state */
if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
{
- ERROR("can't add breakpoint to finish algorithm execution");
+ LOG_ERROR("can't add breakpoint to finish algorithm execution");
return ERROR_TARGET_FAILURE;
}
-
- /* This code relies on the target specific resume() and poll()->debug_entry()
- sequence to write register values to the processor and the read them back */
- target->type->resume(target, 0, entry_point, 1, 1);
- target->type->poll(target);
-
- while (target->state != TARGET_HALTED)
+
+ retval = armv7m_run_and_wait(target, entry_point, timeout_ms, exit_point, armv7m);
+
+ breakpoint_remove(target, exit_point);
+
+ if (retval != ERROR_OK)
{
- usleep(5000);
- target->type->poll(target);
- if ((timeout_ms -= 5) <= 0)
- {
- ERROR("timeout waiting for algorithm to complete, trying to halt target");
- target->type->halt(target);
- timeout_ms = 1000;
- while (target->state != TARGET_HALTED)
- {
- usleep(10000);
- target->type->poll(target);
- if ((timeout_ms -= 10) <= 0)
- {
- ERROR("target didn't reenter debug state, exiting");
- exit(-1);
- }
- }
- armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
- DEBUG("failed algoritm halted at 0x%x ", pc);
- retval = ERROR_TARGET_TIMEOUT;
- }
+ return retval;
}
-
- breakpoint_remove(target, exit_point);
-
+
/* Read memory values to mem_params[] */
for (i = 0; i < num_mem_params; i++)
{
if (mem_params[i].direction != PARAM_OUT)
- target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+ if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value)) != ERROR_OK)
+ {
+ return retval;
+ }
}
-
+
/* Copy core register values to reg_params[] */
for (i = 0; i < num_reg_params; i++)
{
if (reg_params[i].direction != PARAM_OUT)
{
- reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
-
+ reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
+
if (!reg)
{
- ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+ LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
exit(-1);
}
-
+
if (reg->size != reg_params[i].size)
{
- ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
+ LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
exit(-1);
}
-
+
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
}
}
-
+
+ for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
+ {
+ uint32_t regvalue;
+ regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
+ if (regvalue != context[i])
+ {
+ LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", armv7m->core_cache->reg_list[i].name, context[i]);
+ buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
+ armv7m->core_cache->reg_list[i].valid = 1;
+ armv7m->core_cache->reg_list[i].dirty = 1;
+ }
+ }
+
+ armv7m->core_mode = core_mode;
+
return retval;
}
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
-
- USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
- armv7m_state_strings[armv7m->core_state],
- target_debug_reason_strings[target->debug_reason],
- armv7m_mode_strings[armv7m->core_mode],
- armv7m_exception_string(armv7m->exception_number),
- buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
- buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
-
+
+ LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
+ Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
+ armv7m_mode_strings[armv7m->core_mode],
+ armv7m_exception_string(armv7m->exception_number),
+ buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
+ buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
+
return ERROR_OK;
}
reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
int i;
-
+
if (armv7m_core_reg_arch_type == -1)
+ {
armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
-
- /* Build the process context cache */
+ }
+
+ register_init_dummy(&armv7m_gdb_dummy_fps_reg);
+#ifdef ARMV7_GDB_HACKS
+ register_init_dummy(&armv7m_gdb_dummy_cpsr_reg);
+#endif
+ register_init_dummy(&armv7m_gdb_dummy_fp_reg);
+
+ /* Build the process context cache */
cache->name = "arm v7m registers";
cache->next = NULL;
cache->reg_list = reg_list;
cache->num_regs = num_regs;
(*cache_p) = cache;
armv7m->core_cache = cache;
- armv7m->process_context = cache;
-
+
for (i = 0; i < num_regs; i++)
{
arch_info[i] = armv7m_core_reg_list_arch_info[i];
reg_list[i].arch_info = &arch_info[i];
}
- /* Build the debug context cache*/
- cache = malloc(sizeof(reg_cache_t));
- reg_list = malloc(sizeof(reg_t) * num_regs);
-
- cache->name = "arm v7m debug registers";
- cache->next = NULL;
- cache->reg_list = reg_list;
- cache->num_regs = num_regs;
- armv7m->debug_context = cache;
- armv7m->process_context->next = cache;
-
- for (i = 0; i < num_regs; i++)
- {
- reg_list[i].name = armv7m_core_dbgreg_list[i];
- reg_list[i].size = 32;
- reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
- reg_list[i].bitfield_desc = NULL;
- reg_list[i].num_bitfields = 0;
- reg_list[i].arch_type = armv7m_core_reg_arch_type;
- reg_list[i].arch_info = &arch_info[i];
- }
-
return cache;
}
int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
armv7m_build_reg_cache(target);
-
+
return ERROR_OK;
}
int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
{
/* register arch-specific functions */
-
+
target->arch_info = armv7m;
- armv7m->core_state = ARMV7M_STATE_THUMB;
armv7m->read_core_reg = armv7m_read_core_reg;
armv7m->write_core_reg = armv7m_write_core_reg;
-
+
return ERROR_OK;
}
int armv7m_register_commands(struct command_context_s *cmd_ctx)
{
+ command_t *arm_adi_v5_dap_cmd;
+
+ arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "Displays dap info for ap [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "Select a different AP [num] (default 0)");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", handle_dap_apid_command, COMMAND_EXEC, "Displays id reg from AP [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", handle_dap_baseaddr_command, COMMAND_EXEC, "Displays debug base address from AP [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess", handle_dap_memaccess_command, COMMAND_EXEC, "set/get number of extra tck for mem-ap memory bus access [0-255]");
+
return ERROR_OK;
}
-int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
{
working_area_t *crc_algorithm;
armv7m_algorithm_t armv7m_info;
reg_param_t reg_params[2];
int retval;
-
- u16 cortex_m3_crc_code[] = {
+
+ uint16_t cortex_m3_crc_code[] = {
0x4602, /* mov r2, r0 */
0xF04F, 0x30FF, /* mov r0, #0xffffffff */
0x460B, /* mov r3, r1 */
0x5D11, /* ldrb r1, [r2, r4] */
0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
-
+
0xF04F, 0x0500, /* mov r5, #0 */
/* loop: */
0x2800, /* cmp r0, #0 */
0xEA86, 0x0007, /* eor r0, r6, r7 */
0x2D08, /* cmp r5, #8 */
0xD1F4, /* bne loop */
-
+
0xF104, 0x0401, /* add r4, r4, #1 */
/* ncomp: */
0x429C, /* cmp r4, r3 */
0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
};
- int i;
-
+ uint32_t i;
+
if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
-
+
/* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
- target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i]);
-
+ for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(uint16_t)); i++)
+ if ((retval = target_write_u16(target, crc_algorithm->address + i*sizeof(uint16_t), cortex_m3_crc_code[i])) != ERROR_OK)
+ {
+ return retval;
+ }
+
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARMV7M_MODE_ANY;
- armv7m_info.core_state = ARMV7M_STATE_THUMB;
-
+
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
-
+
buf_set_u32(reg_params[0].value, 0, 32, address);
buf_set_u32(reg_params[1].value, 0, 32, count);
-
- if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
+
+ if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
{
- ERROR("error executing cortex_m3 crc algorithm");
+ LOG_ERROR("error executing cortex_m3 crc algorithm");
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
target_free_working_area(target, crc_algorithm);
return retval;
}
-
+
*checksum = buf_get_u32(reg_params[0].value, 0, 32);
-
+
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
-
+
target_free_working_area(target, crc_algorithm);
-
+
return ERROR_OK;
}
+int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
+{
+ working_area_t *erase_check_algorithm;
+ reg_param_t reg_params[3];
+ armv7m_algorithm_t armv7m_info;
+ int retval;
+ uint32_t i;
+
+ uint16_t erase_check_code[] =
+ {
+ /* loop: */
+ 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
+ 0xEA02, 0x0203, /* and r2, r2, r3 */
+ 0x3901, /* subs r1, r1, #1 */
+ 0xD1F9, /* bne loop */
+ /* end: */
+ 0xE7FE, /* b end */
+ };
+
+ /* make sure we have a working area */
+ if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
+ {
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ /* convert flash writing code into a buffer in target endianness */
+ for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint16_t)); i++)
+ target_write_u16(target, erase_check_algorithm->address + i*sizeof(uint16_t), erase_check_code[i]);
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARMV7M_MODE_ANY;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
+ buf_set_u32(reg_params[0].value, 0, 32, address);
+
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
+ buf_set_u32(reg_params[1].value, 0, 32, count);
+
+ init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
+ buf_set_u32(reg_params[2].value, 0, 32, 0xff);
+
+ if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+ erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code)-2), 10000, &armv7m_info)) != ERROR_OK)
+ {
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ target_free_working_area(target, erase_check_algorithm);
+ return 0;
+ }
+
+ *blank = buf_get_u32(reg_params[2].value, 0, 32);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+
+ target_free_working_area(target, erase_check_algorithm);
+
+ return ERROR_OK;
+}
+
+/********************************************************************************************************************
+* Return the debug ap baseaddress in hexadecimal, no extra output to simplify script processing
+*********************************************************************************************************************/
+int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ uint32_t apsel, apselsave, baseaddr;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apsel);
+ }
+
+ dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
+
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apselsave);
+ }
+
+ return retval;
+}
+
+
+/********************************************************************************************************************
+* Return the debug ap id in hexadecimal, no extra output to simplify script processing
+*********************************************************************************************************************/
+extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ uint32_t apsel, apselsave, apid;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apsel);
+ }
+
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8" PRIx32 "", apid);
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apselsave);
+ }
+
+ return retval;
+}
+
+int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ uint32_t apsel, apid;
+ int retval;
+
+ apsel = 0;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ dap_ap_select(swjdp, apsel);
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8" PRIx32 "", (int)apsel, apid);
+
+ return retval;
+}
+
+int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ uint32_t memaccess_tck;
+
+ memaccess_tck = swjdp->memaccess_tck;
+ if (argc > 0)
+ {
+ memaccess_tck = strtoul(args[0], NULL, 0);
+ }
+
+ swjdp->memaccess_tck = memaccess_tck;
+ command_print(cmd_ctx, "memory bus access delay set to %i tck", (int)(swjdp->memaccess_tck));
+
+ return ERROR_OK;
+}
+
+int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ int retval;
+ uint32_t apsel;
+
+ apsel = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ retval = dap_info_command(cmd_ctx, swjdp, apsel);
+
+ return retval;
+}
+
projects / fw / openocd / blobdiff