* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
* *
- * ARMv7-M Architecture, Application Level Reference Manual *
+ * ARMv7-M Architecture, Application Level Reference Manual *
* ARM DDI 0405C (September 2008) *
* *
***************************************************************************/
#include "config.h"
#endif
+#include "breakpoints.h"
+#include "target.h"
#include "armv7m.h"
+#include "algorithm.h"
+#include "register.h"
#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-char* armv7m_mode_strings[] =
+/** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
+char *armv7m_mode_strings[] =
{
"Thread", "Thread (User)", "Handler",
};
"DebugMonitor", "RESERVED", "PendSV", "SysTick"
};
-uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+/* FIXME these dummies are IDENTICAL to the armv4_5, arm11, and armv7a
+ * ones... except for naming/scoping
+ */
+static uint8_t armv7m_gdb_dummy_fp_value[12];
-reg_t armv7m_gdb_dummy_fp_reg =
+static struct reg armv7m_gdb_dummy_fp_reg =
{
- "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
+ .name = "GDB dummy floating-point register",
+ .value = armv7m_gdb_dummy_fp_value,
+ .dirty = 0,
+ .valid = 1,
+ .size = 96,
+ .arch_info = NULL,
+ .arch_type = 0,
};
-uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+static uint8_t armv7m_gdb_dummy_fps_value[4];
-reg_t armv7m_gdb_dummy_fps_reg =
+static struct reg armv7m_gdb_dummy_fps_reg =
{
- "GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
+ .name = "GDB dummy floating-point status register",
+ .value = armv7m_gdb_dummy_fps_value,
+ .dirty = 0,
+ .valid = 1,
+ .size = 32,
+ .arch_info = NULL,
+ .arch_type = 0,
};
#ifdef ARMV7_GDB_HACKS
uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
-reg_t armv7m_gdb_dummy_cpsr_reg =
+struct reg armv7m_gdb_dummy_cpsr_reg =
{
- "GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
+ .name = "GDB dummy cpsr register",
+ .value = armv7m_gdb_dummy_cpsr_value,
+ .dirty = 0,
+ .valid = 1,
+ .size = 32,
+ .arch_info = NULL,
+ .arch_type = 0,
};
#endif
* These registers are not memory-mapped. The ARMv7-M profile includes
* memory mapped registers too, such as for the NVIC (interrupt controller)
* and SysTick (timer) modules; those can mostly be treated as peripherals.
+ *
+ * The ARMv6-M profile is almost identical in this respect, except that it
+ * doesn't include basepri or faultmask registers.
*/
static const struct {
unsigned id;
char *name;
+ unsigned bits;
} armv7m_regs[] = {
- { ARMV7M_R0, "r0" },
- { ARMV7M_R1, "r1" },
- { ARMV7M_R2, "r2" },
- { ARMV7M_R3, "r3" },
-
- { ARMV7M_R4, "r4" },
- { ARMV7M_R5, "r5" },
- { ARMV7M_R6, "r6" },
- { ARMV7M_R7, "r7" },
-
- { ARMV7M_R8, "r8" },
- { ARMV7M_R9, "r9" },
- { ARMV7M_R10, "r10" },
- { ARMV7M_R11, "r11" },
-
- { ARMV7M_R12, "r12" },
- { ARMV7M_R13, "sp" },
- { ARMV7M_R14, "lr" },
- { ARMV7M_PC, "pc" },
-
- { ARMV7M_xPSR, "xPSR" },
- { ARMV7M_MSP, "msp" },
- { ARMV7M_PSP, "psp" },
-
- { ARMV7M_PRIMASK, "primask" },
- { ARMV7M_BASEPRI, "basepri" },
- { ARMV7M_FAULTMASK, "faultmask" },
- { ARMV7M_CONTROL, "control" },
+ { ARMV7M_R0, "r0", 32 },
+ { ARMV7M_R1, "r1", 32 },
+ { ARMV7M_R2, "r2", 32 },
+ { ARMV7M_R3, "r3", 32 },
+
+ { ARMV7M_R4, "r4", 32 },
+ { ARMV7M_R5, "r5", 32 },
+ { ARMV7M_R6, "r6", 32 },
+ { ARMV7M_R7, "r7", 32 },
+
+ { ARMV7M_R8, "r8", 32 },
+ { ARMV7M_R9, "r9", 32 },
+ { ARMV7M_R10, "r10", 32 },
+ { ARMV7M_R11, "r11", 32 },
+
+ { ARMV7M_R12, "r12", 32 },
+ { ARMV7M_R13, "sp", 32 },
+ { ARMV7M_R14, "lr", 32 },
+ { ARMV7M_PC, "pc", 32 },
+
+ { ARMV7M_xPSR, "xPSR", 32 },
+ { ARMV7M_MSP, "msp", 32 },
+ { ARMV7M_PSP, "psp", 32 },
+
+ { ARMV7M_PRIMASK, "primask", 1 },
+ { ARMV7M_BASEPRI, "basepri", 8 },
+ { ARMV7M_FAULTMASK, "faultmask", 1 },
+ { ARMV7M_CONTROL, "control", 2 },
};
#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
-int armv7m_core_reg_arch_type = -1;
-int armv7m_dummy_core_reg_arch_type = -1;
+static int armv7m_core_reg_arch_type = -1;
-int armv7m_restore_context(target_t *target)
+/**
+ * Restores target context using the cache of core registers set up
+ * by armv7m_build_reg_cache(), calling optional core-specific hooks.
+ */
+int armv7m_restore_context(struct target *target)
{
int i;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
LOG_DEBUG(" ");
}
/* Core state functions */
+
+/**
+ * Maps ISR number (from xPSR) to name.
+ * Note that while names and meanings for the first sixteen are standardized
+ * (with zero not a true exception), external interrupts are only numbered.
+ * They are assigned by vendors, which generally assign different numbers to
+ * peripherals (such as UART0 or a USB peripheral controller).
+ */
char *armv7m_exception_string(int number)
{
static char enamebuf[32];
return enamebuf;
}
-int armv7m_get_core_reg(reg_t *reg)
+static int armv7m_get_core_reg(struct reg *reg)
{
int retval;
- armv7m_core_reg_t *armv7m_reg = reg->arch_info;
- target_t *target = armv7m_reg->target;
- armv7m_common_t *armv7m_target = target->arch_info;
+ struct armv7m_core_reg *armv7m_reg = reg->arch_info;
+ struct target *target = armv7m_reg->target;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
if (target->state != TARGET_HALTED)
{
return ERROR_TARGET_NOT_HALTED;
}
- retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
+ retval = armv7m->read_core_reg(target, armv7m_reg->num);
return retval;
}
-int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
+static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
{
- armv7m_core_reg_t *armv7m_reg = reg->arch_info;
- target_t *target = armv7m_reg->target;
+ struct armv7m_core_reg *armv7m_reg = reg->arch_info;
+ struct target *target = armv7m_reg->target;
uint32_t value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
return ERROR_OK;
}
-int armv7m_read_core_reg(struct target_s *target, int num)
+static int armv7m_read_core_reg(struct target *target, int num)
{
uint32_t reg_value;
int retval;
- armv7m_core_reg_t * armv7m_core_reg;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
+ struct armv7m_core_reg * armv7m_core_reg;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
if ((num < 0) || (num >= ARMV7M_NUM_REGS))
return ERROR_INVALID_ARGUMENTS;
return retval;
}
-int armv7m_write_core_reg(struct target_s *target, int num)
+static int armv7m_write_core_reg(struct target *target, int num)
{
int retval;
uint32_t reg_value;
- armv7m_core_reg_t *armv7m_core_reg;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
+ struct armv7m_core_reg *armv7m_core_reg;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
if ((num < 0) || (num >= ARMV7M_NUM_REGS))
return ERROR_INVALID_ARGUMENTS;
return ERROR_OK;
}
-int armv7m_invalidate_core_regs(target_t *target)
+/** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
+int armv7m_invalidate_core_regs(struct target *target)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
int i;
for (i = 0; i < armv7m->core_cache->num_regs; i++)
return ERROR_OK;
}
-int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
+/**
+ * Returns generic ARM userspace registers to GDB.
+ * GDB doesn't quite understand that most ARMs don't have floating point
+ * hardware, so this also fakes a set of long-obsolete FPA registers that
+ * are not used in EABI based software stacks.
+ */
+int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
int i;
*reg_list_size = 26;
- *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
+ *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
/*
* GDB register packet format for ARM:
}
/* run to exit point. return error if exit point was not reached. */
-static int armv7m_run_and_wait(struct target_s *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, armv7m_common_t *armv7m)
+static int armv7m_run_and_wait(struct target *target, uint32_t entry_point, int timeout_ms, uint32_t exit_point, struct armv7m_common *armv7m)
{
uint32_t pc;
int retval;
return ERROR_OK;
}
-int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
+/** Runs a Thumb algorithm in the target. */
+int armv7m_run_algorithm(struct target *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ uint32_t entry_point, uint32_t exit_point,
+ int timeout_ms, void *arch_info)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
enum armv7m_mode core_mode = armv7m->core_mode;
int retval = ERROR_OK;
int i;
for (i = 0; i < num_reg_params; i++)
{
- reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
// uint32_t regvalue;
if (!reg)
armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
}
+ /* REVISIT speed things up (3% or so in one case) by requiring
+ * algorithms to include a BKPT instruction at each exit point.
+ * This eliminates overheads of adding/removing a breakpoint.
+ */
+
/* ARMV7M always runs in Thumb state */
if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
{
{
if (reg_params[i].direction != PARAM_OUT)
{
- reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
}
}
- for (i = ARMV7M_NUM_REGS; i >= 0; i--)
+ for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
{
uint32_t regvalue;
regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
return retval;
}
-int armv7m_arch_state(struct target_s *target)
+/** Logs summary of ARMv7-M state for a halted target. */
+int armv7m_arch_state(struct target *target)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
uint32_t ctrl, sp;
ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
return ERROR_OK;
}
-reg_cache_t *armv7m_build_reg_cache(target_t *target)
+/** Builds cache of architecturally defined registers. */
+struct reg_cache *armv7m_build_reg_cache(struct target *target)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
+ struct armv7m_common *armv7m = target_to_armv7m(target);
int num_regs = ARMV7M_NUM_REGS;
- reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
- reg_cache_t *cache = malloc(sizeof(reg_cache_t));
- reg_t *reg_list = calloc(num_regs, sizeof(reg_t));
- armv7m_core_reg_t *arch_info = calloc(num_regs, sizeof(armv7m_core_reg_t));
+ struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
+ struct reg_cache *cache = malloc(sizeof(struct reg_cache));
+ struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
+ struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
int i;
if (armv7m_core_reg_arch_type == -1)
arch_info[i].target = target;
arch_info[i].armv7m_common = armv7m;
reg_list[i].name = armv7m_regs[i].name;
- reg_list[i].size = 32;
+ reg_list[i].size = armv7m_regs[i].bits;
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
- reg_list[i].bitfield_desc = NULL;
- reg_list[i].num_bitfields = 0;
reg_list[i].arch_type = armv7m_core_reg_arch_type;
reg_list[i].arch_info = &arch_info[i];
}
return cache;
}
-int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
-{
- armv7m_build_reg_cache(target);
-
- return ERROR_OK;
-}
-
-int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
+/** Sets up target as a generic ARMv7-M core */
+int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
{
/* register arch-specific functions */
return ERROR_OK;
}
-int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
+/** Generates a CRC32 checksum of a memory region. */
+int armv7m_checksum_memory(struct target *target,
+ uint32_t address, uint32_t count, uint32_t* checksum)
{
- working_area_t *crc_algorithm;
- armv7m_algorithm_t armv7m_info;
- reg_param_t reg_params[2];
+ struct working_area *crc_algorithm;
+ struct armv7m_algorithm armv7m_info;
+ struct reg_param reg_params[2];
int retval;
- uint16_t cortex_m3_crc_code[] = {
+ static const uint16_t cortex_m3_crc_code[] = {
0x4602, /* mov r2, r0 */
0xF04F, 0x30FF, /* mov r0, #0xffffffff */
0x460B, /* mov r3, r1 */
return ERROR_OK;
}
-int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
+/** Checks whether a memory region is zeroed. */
+int armv7m_blank_check_memory(struct target *target,
+ uint32_t address, uint32_t count, uint32_t* blank)
{
- working_area_t *erase_check_algorithm;
- reg_param_t reg_params[3];
- armv7m_algorithm_t armv7m_info;
+ struct working_area *erase_check_algorithm;
+ struct reg_param reg_params[3];
+ struct armv7m_algorithm armv7m_info;
int retval;
uint32_t i;
- uint16_t erase_check_code[] =
+ static const uint16_t erase_check_code[] =
{
- /* loop: */
- 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
- 0xEA02, 0x0203, /* and r2, r2, r3 */
- 0x3901, /* subs r1, r1, #1 */
- 0xD1F9, /* bne loop */
- /* end: */
- 0xE7FE, /* b end */
+ /* loop: */
+ 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
+ 0xEA02, 0x0203, /* and r2, r2, r3 */
+ 0x3901, /* subs r1, r1, #1 */
+ 0xD1F9, /* bne loop */
+ /* end: */
+ 0xE7FE, /* b end */
};
/* make sure we have a working area */
return ERROR_OK;
}
+/*--------------------------------------------------------------------------*/
+
+/*
+ * Only stuff below this line should need to verify that its target
+ * is an ARMv7-M node.
+ *
+ * FIXME yet none of it _does_ verify target types yet!
+ */
+
+
/*
* Return the debug ap baseaddress in hexadecimal;
* no extra output to simplify script processing
*/
-static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx,
- char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_dap_baseaddr_command)
{
- target_t *target = get_current_target(cmd_ctx);
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct target *target = get_current_target(cmd_ctx);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
uint32_t apsel, apselsave, baseaddr;
int retval;
- apsel = swjdp->apsel;
apselsave = swjdp->apsel;
- if (argc > 0)
- {
- apsel = strtoul(args[0], NULL, 0);
+ switch (argc) {
+ case 0:
+ apsel = swjdp->apsel;
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, args[0], apsel);
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
+
if (apselsave != apsel)
- {
dap_ap_select(swjdp, apsel);
- }
dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
retval = swjdp_transaction_endcheck(swjdp);
command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
if (apselsave != apsel)
- {
dap_ap_select(swjdp, apselsave);
- }
return retval;
}
-
/*
* Return the debug ap id in hexadecimal;
* no extra output to simplify script processing
*/
-extern int handle_dap_apid_command(struct command_context_s *cmd_ctx,
- char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_dap_apid_command)
{
- target_t *target = get_current_target(cmd_ctx);
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct target *target = get_current_target(cmd_ctx);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
- return dap_apid_command(cmd_ctx, swjdp, args, argc);
+ return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
}
-static int handle_dap_apsel_command(struct command_context_s *cmd_ctx,
- char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_dap_apsel_command)
{
- target_t *target = get_current_target(cmd_ctx);
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct target *target = get_current_target(cmd_ctx);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
- return dap_apsel_command(cmd_ctx, swjdp, args, argc);
+ return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
}
-static int handle_dap_memaccess_command(struct command_context_s *cmd_ctx,
- char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_dap_memaccess_command)
{
- target_t *target = get_current_target(cmd_ctx);
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct target *target = get_current_target(cmd_ctx);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
- return dap_memaccess_command(cmd_ctx, swjdp, args, argc);
+ return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
}
-static int handle_dap_info_command(struct command_context_s *cmd_ctx,
- char *cmd, char **args, int argc)
+COMMAND_HANDLER(handle_dap_info_command)
{
- target_t *target = get_current_target(cmd_ctx);
- armv7m_common_t *armv7m = target->arch_info;
- swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ struct target *target = get_current_target(cmd_ctx);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct swjdp_common *swjdp = &armv7m->swjdp_info;
uint32_t apsel;
- apsel = swjdp->apsel;
- if (argc > 0)
- apsel = strtoul(args[0], NULL, 0);
+ switch (argc) {
+ case 0:
+ apsel = swjdp->apsel;
+ break;
+ case 1:
+ COMMAND_PARSE_NUMBER(u32, args[0], apsel);
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
return dap_info_command(cmd_ctx, swjdp, apsel);
}
-int armv7m_register_commands(struct command_context_s *cmd_ctx)
+/** Registers commands used to access DAP resources. */
+int armv7m_register_commands(struct command_context *cmd_ctx)
{
- command_t *arm_adi_v5_dap_cmd;
+ struct command *arm_adi_v5_dap_cmd;
arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
NULL, COMMAND_ANY,
projects / fw / openocd / blobdiff