MIPS: merge mips fast_data patch from David N. Claffey
[fw/openocd] / src / target / armv7m.c
index fc3f47ccdb46e6f58b95e9223198622b972ad29d..9d8132d43b665c635f6ad506f1f30c836f9a48de 100644 (file)
@@ -480,8 +480,7 @@ int armv7m_arch_state(struct target *target)
 
        LOG_USER("target halted due to %s, current mode: %s %s\n"
                "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
-               Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-                               target->debug_reason)->name,
+               debug_reason_name(target),
                armv7m_mode_strings[armv7m->core_mode],
                armv7m_exception_string(armv7m->exception_number),
                buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
@@ -732,7 +731,12 @@ COMMAND_HANDLER(handle_dap_baseaddr_command)
        if (apselsave != apsel)
                dap_ap_select(swjdp, apsel);
 
-       dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
+       /* NOTE:  assumes we're talking to a MEM-AP, which
+        * has a base address.  There are other kinds of AP,
+        * though they're not common for now.  This should
+        * use the ID register to verify it's a MEM-AP.
+        */
+       dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
        retval = swjdp_transaction_endcheck(swjdp);
        command_print(CMD_CTX, "0x%8.8" PRIx32 "", baseaddr);
 
@@ -835,7 +839,7 @@ static const struct command_registration armv7m_exec_command_handlers[] = {
 const struct command_registration armv7m_command_handlers[] = {
        {
                .name = "dap",
-               .mode = COMMAND_ANY,
+               .mode = COMMAND_EXEC,
                .help = "Cortex DAP command group",
                .chain = armv7m_exec_command_handlers,
        },