* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
* *
- * ARMv7-M Architecture, Application Level Reference Manual *
+ * ARMv7-M Architecture, Application Level Reference Manual *
* ARM DDI 0405C (September 2008) *
* *
***************************************************************************/
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-char* armv7m_mode_strings[] =
+/** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
+char *armv7m_mode_strings[] =
{
"Thread", "Thread (User)", "Handler",
};
"DebugMonitor", "RESERVED", "PendSV", "SysTick"
};
-uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+static uint8_t armv7m_gdb_dummy_fp_value[12] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+};
-reg_t armv7m_gdb_dummy_fp_reg =
+static reg_t armv7m_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
-uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
+static uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
-reg_t armv7m_gdb_dummy_fps_reg =
+static reg_t armv7m_gdb_dummy_fps_reg =
{
"GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
* These registers are not memory-mapped. The ARMv7-M profile includes
* memory mapped registers too, such as for the NVIC (interrupt controller)
* and SysTick (timer) modules; those can mostly be treated as peripherals.
+ *
+ * The ARMv6-M profile is almost identical in this respect, except that it
+ * doesn't include basepri or faultmask registers.
*/
static const struct {
unsigned id;
char *name;
+ unsigned bits;
} armv7m_regs[] = {
- { ARMV7M_R0, "r0" },
- { ARMV7M_R1, "r1" },
- { ARMV7M_R2, "r2" },
- { ARMV7M_R3, "r3" },
-
- { ARMV7M_R4, "r4" },
- { ARMV7M_R5, "r5" },
- { ARMV7M_R6, "r6" },
- { ARMV7M_R7, "r7" },
-
- { ARMV7M_R8, "r8" },
- { ARMV7M_R9, "r9" },
- { ARMV7M_R10, "r10" },
- { ARMV7M_R11, "r11" },
-
- { ARMV7M_R12, "r12" },
- { ARMV7M_R13, "sp" },
- { ARMV7M_R14, "lr" },
- { ARMV7M_PC, "pc" },
-
- { ARMV7M_xPSR, "xPSR" },
- { ARMV7M_MSP, "msp" },
- { ARMV7M_PSP, "psp" },
-
- { ARMV7M_PRIMASK, "primask" },
- { ARMV7M_BASEPRI, "basepri" },
- { ARMV7M_FAULTMASK, "faultmask" },
- { ARMV7M_CONTROL, "control" },
+ { ARMV7M_R0, "r0", 32 },
+ { ARMV7M_R1, "r1", 32 },
+ { ARMV7M_R2, "r2", 32 },
+ { ARMV7M_R3, "r3", 32 },
+
+ { ARMV7M_R4, "r4", 32 },
+ { ARMV7M_R5, "r5", 32 },
+ { ARMV7M_R6, "r6", 32 },
+ { ARMV7M_R7, "r7", 32 },
+
+ { ARMV7M_R8, "r8", 32 },
+ { ARMV7M_R9, "r9", 32 },
+ { ARMV7M_R10, "r10", 32 },
+ { ARMV7M_R11, "r11", 32 },
+
+ { ARMV7M_R12, "r12", 32 },
+ { ARMV7M_R13, "sp", 32 },
+ { ARMV7M_R14, "lr", 32 },
+ { ARMV7M_PC, "pc", 32 },
+
+ { ARMV7M_xPSR, "xPSR", 32 },
+ { ARMV7M_MSP, "msp", 32 },
+ { ARMV7M_PSP, "psp", 32 },
+
+ { ARMV7M_PRIMASK, "primask", 1 },
+ { ARMV7M_BASEPRI, "basepri", 8 },
+ { ARMV7M_FAULTMASK, "faultmask", 1 },
+ { ARMV7M_CONTROL, "control", 2 },
};
#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
-int armv7m_core_reg_arch_type = -1;
-int armv7m_dummy_core_reg_arch_type = -1;
+static int armv7m_core_reg_arch_type = -1;
+/**
+ * Restores target context using the cache of core registers set up
+ * by armv7m_build_reg_cache(), calling optional core-specific hooks.
+ */
int armv7m_restore_context(target_t *target)
{
int i;
}
/* Core state functions */
+
+/**
+ * Maps ISR number (from xPSR) to name.
+ * Note that while names and meanings for the first sixteen are standardized
+ * (with zero not a true exception), external interrupts are only numbered.
+ * They are assigned by vendors, which generally assign different numbers to
+ * peripherals (such as UART0 or a USB peripheral controller).
+ */
char *armv7m_exception_string(int number)
{
static char enamebuf[32];
return enamebuf;
}
-int armv7m_get_core_reg(reg_t *reg)
+static int armv7m_get_core_reg(reg_t *reg)
{
int retval;
armv7m_core_reg_t *armv7m_reg = reg->arch_info;
return retval;
}
-int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
+static int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
{
armv7m_core_reg_t *armv7m_reg = reg->arch_info;
target_t *target = armv7m_reg->target;
return ERROR_OK;
}
-int armv7m_read_core_reg(struct target_s *target, int num)
+static int armv7m_read_core_reg(struct target_s *target, int num)
{
uint32_t reg_value;
int retval;
return retval;
}
-int armv7m_write_core_reg(struct target_s *target, int num)
+static int armv7m_write_core_reg(struct target_s *target, int num)
{
int retval;
uint32_t reg_value;
return ERROR_OK;
}
+/** Invalidates cache of core registers set up by armv7m_build_reg_cache(). */
int armv7m_invalidate_core_regs(target_t *target)
{
/* get pointers to arch-specific information */
return ERROR_OK;
}
+/**
+ * Returns generic ARM userspace registers to GDB.
+ * GDB doesn't quite understand that most ARMs don't have floating point
+ * hardware, so this also fakes a set of long-obsolete FPA registers that
+ * are not used in EABI based software stacks.
+ */
int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
{
/* get pointers to arch-specific information */
return ERROR_OK;
}
-int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
+/** Runs a Thumb algorithm in the target. */
+int armv7m_run_algorithm(struct target_s *target,
+ int num_mem_params, mem_param_t *mem_params,
+ int num_reg_params, reg_param_t *reg_params,
+ uint32_t entry_point, uint32_t exit_point,
+ int timeout_ms, void *arch_info)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
}
+ /* REVISIT speed things up (3% or so in one case) by requiring
+ * algorithms to include a BKPT instruction at each exit point.
+ * This eliminates overheads of adding/removing a breakpoint.
+ */
+
/* ARMV7M always runs in Thumb state */
if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
{
}
}
- for (i = ARMV7M_NUM_REGS; i >= 0; i--)
+ for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
{
uint32_t regvalue;
regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
return retval;
}
+/** Logs summary of ARMv7-M state for a halted target. */
int armv7m_arch_state(struct target_s *target)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
+ uint32_t ctrl, sp;
+
+ ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
+ sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
LOG_USER("target halted due to %s, current mode: %s %s\n"
- "xPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32,
- Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
+ "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
+ Jim_Nvp_value2name_simple(nvp_target_debug_reason,
+ target->debug_reason)->name,
armv7m_mode_strings[armv7m->core_mode],
armv7m_exception_string(armv7m->exception_number),
buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
- buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32));
+ buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32),
+ (ctrl & 0x02) ? 'p' : 'm',
+ sp);
return ERROR_OK;
}
+/** Builds cache of architecturally defined registers. */
reg_cache_t *armv7m_build_reg_cache(target_t *target)
{
/* get pointers to arch-specific information */
arch_info[i].target = target;
arch_info[i].armv7m_common = armv7m;
reg_list[i].name = armv7m_regs[i].name;
- reg_list[i].size = 32;
+ reg_list[i].size = armv7m_regs[i].bits;
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
return cache;
}
-int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
-{
- armv7m_build_reg_cache(target);
-
- return ERROR_OK;
-}
-
+/** Sets up target as a generic ARMv7-M core */
int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
{
/* register arch-specific functions */
return ERROR_OK;
}
-int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum)
+/** Generates a CRC32 checksum of a memory region. */
+int armv7m_checksum_memory(struct target_s *target,
+ uint32_t address, uint32_t count, uint32_t* checksum)
{
working_area_t *crc_algorithm;
armv7m_algorithm_t armv7m_info;
reg_param_t reg_params[2];
int retval;
- uint16_t cortex_m3_crc_code[] = {
+ static const uint16_t cortex_m3_crc_code[] = {
0x4602, /* mov r2, r0 */
0xF04F, 0x30FF, /* mov r0, #0xffffffff */
0x460B, /* mov r3, r1 */
return ERROR_OK;
}
-int armv7m_blank_check_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* blank)
+/** Checks whether a memory region is zeroed. */
+int armv7m_blank_check_memory(struct target_s *target,
+ uint32_t address, uint32_t count, uint32_t* blank)
{
working_area_t *erase_check_algorithm;
reg_param_t reg_params[3];
int retval;
uint32_t i;
- uint16_t erase_check_code[] =
+ static const uint16_t erase_check_code[] =
{
- /* loop: */
- 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
- 0xEA02, 0x0203, /* and r2, r2, r3 */
- 0x3901, /* subs r1, r1, #1 */
- 0xD1F9, /* bne loop */
- /* end: */
- 0xE7FE, /* b end */
+ /* loop: */
+ 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
+ 0xEA02, 0x0203, /* and r2, r2, r3 */
+ 0x3901, /* subs r1, r1, #1 */
+ 0xD1F9, /* bne loop */
+ /* end: */
+ 0xE7FE, /* b end */
};
/* make sure we have a working area */
return retval;
}
-
/*
* Return the debug ap id in hexadecimal;
* no extra output to simplify script processing
*/
-extern int handle_dap_apid_command(struct command_context_s *cmd_ctx,
+static int handle_dap_apid_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
return dap_info_command(cmd_ctx, swjdp, apsel);
}
+/** Registers commands used to access DAP resources. */
int armv7m_register_commands(struct command_context_s *cmd_ctx)
{
command_t *arm_adi_v5_dap_cmd;
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