/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
+ * *
* Copyright (C) 2006 by Magnus Lundin *
* lundin@mlu.mine.nu *
* *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2007,2008 Øyvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
+ * Copyright (C) 2018 by Liviu Ionescu *
+ * <ilg@livius.net> *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ * *
+ * ARMv7-M Architecture, Application Level Reference Manual *
+ * ARM DDI 0405C (September 2008) *
+ * *
***************************************************************************/
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
-#include "replacements.h"
-
+#include "breakpoints.h"
#include "armv7m.h"
+#include "algorithm.h"
#include "register.h"
-#include "target.h"
-#include "log.h"
-#include "jtag.h"
-#include "arm_jtag.h"
-
-#include <stdlib.h>
-#include <string.h>
+#include "semihosting_common.h"
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
-char* armv7m_mode_strings[] =
-{
- "Handler", "Thread"
-};
-
-char* armv7m_state_strings[] =
-{
- "Thumb", "Debug"
-};
-
-char* armv7m_exception_strings[] =
-{
- "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
- "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
-};
-
-char* armv7m_core_reg_list[] =
-{
- /* Registers accessed through core debug */
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
- "sp", "lr", "pc",
- "xPSR", "msp", "psp",
- /* Registers accessed through MSR instructions */
-// "apsr", "iapsr", "ipsr", "epsr",
- "primask", "basepri", "faultmask", "control"
+static const char * const armv7m_exception_strings[] = {
+ "", "Reset", "NMI", "HardFault",
+ "MemManage", "BusFault", "UsageFault", "RESERVED",
+ "RESERVED", "RESERVED", "RESERVED", "SVCall",
+ "DebugMonitor", "RESERVED", "PendSV", "SysTick"
};
-char* armv7m_core_dbgreg_list[] =
-{
- /* Registers accessed through core debug */
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
- "sp", "lr", "pc",
- "xPSR", "msp", "psp",
- /* Registers accessed through MSR instructions */
-// "dbg_apsr", "iapsr", "ipsr", "epsr",
- "primask", "basepri", "faultmask", "dbg_control"
+/* PSP is used in some thread modes */
+const int armv7m_psp_reg_map[ARMV7M_NUM_CORE_REGS] = {
+ ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
+ ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
+ ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
+ ARMV7M_R12, ARMV7M_PSP, ARMV7M_R14, ARMV7M_PC,
+ ARMV7M_xPSR,
};
-u8 armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-
-reg_t armv7m_gdb_dummy_fp_reg =
-{
- "GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
+/* MSP is used in handler and some thread modes */
+const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
+ ARMV7M_R0, ARMV7M_R1, ARMV7M_R2, ARMV7M_R3,
+ ARMV7M_R4, ARMV7M_R5, ARMV7M_R6, ARMV7M_R7,
+ ARMV7M_R8, ARMV7M_R9, ARMV7M_R10, ARMV7M_R11,
+ ARMV7M_R12, ARMV7M_MSP, ARMV7M_R14, ARMV7M_PC,
+ ARMV7M_xPSR,
};
-armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
-{
- /* CORE_GP are accesible using the core debug registers */
- {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
- {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL},
-
- {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */
- {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
- {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
-
- /* CORE_SP are accesible using MSR and MRS instructions */
-// {0x00, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* APSR */
-// {0x01, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IAPSR */
-// {0x05, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* IPSR */
-// {0x06, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* EPSR */
-
- {0x10, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
- {0x11, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
- {0x13, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
- {0x14, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
+/*
+ * These registers are not memory-mapped. The ARMv7-M profile includes
+ * memory mapped registers too, such as for the NVIC (interrupt controller)
+ * and SysTick (timer) modules; those can mostly be treated as peripherals.
+ *
+ * The ARMv6-M profile is almost identical in this respect, except that it
+ * doesn't include basepri or faultmask registers.
+ */
+static const struct {
+ unsigned id;
+ const char *name;
+ unsigned bits;
+ enum reg_type type;
+ const char *group;
+ const char *feature;
+} armv7m_regs[] = {
+ { ARMV7M_R0, "r0", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R1, "r1", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R2, "r2", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R3, "r3", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R4, "r4", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R5, "r5", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R6, "r6", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R7, "r7", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R8, "r8", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R9, "r9", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R10, "r10", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R11, "r11", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R12, "r12", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R13, "sp", 32, REG_TYPE_DATA_PTR, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_R14, "lr", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_PC, "pc", 32, REG_TYPE_CODE_PTR, "general", "org.gnu.gdb.arm.m-profile" },
+ { ARMV7M_xPSR, "xPSR", 32, REG_TYPE_INT, "general", "org.gnu.gdb.arm.m-profile" },
+
+ { ARMV7M_MSP, "msp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
+ { ARMV7M_PSP, "psp", 32, REG_TYPE_DATA_PTR, "system", "org.gnu.gdb.arm.m-system" },
+
+ { ARMV7M_PRIMASK, "primask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+ { ARMV7M_BASEPRI, "basepri", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+ { ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+ { ARMV7M_CONTROL, "control", 2, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+
+ { ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D1, "d1", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D2, "d2", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D3, "d3", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D4, "d4", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D5, "d5", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D6, "d6", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D7, "d7", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D8, "d8", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D9, "d9", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D10, "d10", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D11, "d11", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D12, "d12", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D13, "d13", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D14, "d14", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+ { ARMV7M_D15, "d15", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
+
+ { ARMV7M_FPSCR, "fpscr", 32, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp" },
};
-int armv7m_core_reg_arch_type = -1;
-
-/* Keep different contexts for the process being debugged and debug algorithms */
-enum armv7m_runcontext armv7m_get_context(target_t *target)
-{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
- if (armv7m->process_context == armv7m->core_cache)
- return ARMV7M_PROCESS_CONTEXT;
- if (armv7m->debug_context == armv7m->core_cache)
- return ARMV7M_DEBUG_CONTEXT;
-
- ERROR("Invalid runcontext");
- exit(-1);
-}
+#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
-int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
+/**
+ * Restores target context using the cache of core registers set up
+ * by armv7m_build_reg_cache(), calling optional core-specific hooks.
+ */
+int armv7m_restore_context(struct target *target)
{
int i;
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
- if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET))
- {
- WARNING("target not halted, switch context ");
- return ERROR_TARGET_NOT_HALTED;
- }
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct reg_cache *cache = armv7m->arm.core_cache;
- if (new_ctx == armv7m_get_context(target))
- return ERROR_OK;
-
- switch (new_ctx)
- {
- case ARMV7M_PROCESS_CONTEXT:
- armv7m->core_cache = armv7m->process_context;
- break;
- case ARMV7M_DEBUG_CONTEXT:
- armv7m->core_cache = armv7m->debug_context;
- break;
- default:
- ERROR("Invalid runcontext");
- exit(-1);
- }
- /* Mark registers in new context as dirty to force reload when run */
-
- for (i = 0; i < armv7m->core_cache->num_regs-1; i++) /* EXCLUDE CONTROL TODOLATER : CHECK THIS */
- {
- armv7m->core_cache->reg_list[i].dirty = 1;
- }
-
- return ERROR_OK;
-}
-
-int armv7m_restore_context(target_t *target)
-{
- int i;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
- DEBUG(" ");
+ LOG_DEBUG(" ");
if (armv7m->pre_restore_context)
armv7m->pre_restore_context(target);
-
- for (i = ARMV7NUMCOREREGS-1; i >= 0; i--)
- {
- if (armv7m->core_cache->reg_list[i].dirty)
- {
- armv7m->write_core_reg(target, i);
+
+ for (i = cache->num_regs - 1; i >= 0; i--) {
+ if (cache->reg_list[i].dirty) {
+ armv7m->arm.write_core_reg(target, &cache->reg_list[i], i,
+ ARM_MODE_ANY, cache->reg_list[i].value);
}
}
-
- if (armv7m->post_restore_context)
- armv7m->post_restore_context(target);
-
- return ERROR_OK;
-}
+ return ERROR_OK;
+}
/* Core state functions */
-char enamebuf[32];
-char *armv7m_exception_string(int number)
+
+/**
+ * Maps ISR number (from xPSR) to name.
+ * Note that while names and meanings for the first sixteen are standardized
+ * (with zero not a true exception), external interrupts are only numbered.
+ * They are assigned by vendors, which generally assign different numbers to
+ * peripherals (such as UART0 or a USB peripheral controller).
+ */
+const char *armv7m_exception_string(int number)
{
+ static char enamebuf[32];
+
if ((number < 0) | (number > 511))
return "Invalid exception";
if (number < 16)
return enamebuf;
}
-int armv7m_get_core_reg(reg_t *reg)
+static int armv7m_get_core_reg(struct reg *reg)
{
int retval;
- armv7m_core_reg_t *armv7m_reg = reg->arch_info;
- target_t *target = armv7m_reg->target;
- armv7m_common_t *armv7m_target = target->arch_info;
-
+ struct arm_reg *armv7m_reg = reg->arch_info;
+ struct target *target = armv7m_reg->target;
+ struct arm *arm = target_to_arm(target);
+
if (target->state != TARGET_HALTED)
- {
return ERROR_TARGET_NOT_HALTED;
- }
- retval = armv7m_target->read_core_reg(target, armv7m_reg->num);
-
+ retval = arm->read_core_reg(target, reg, reg->number, arm->core_mode);
+
return retval;
}
-int armv7m_set_core_reg(reg_t *reg, u8 *buf)
+static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
{
- armv7m_core_reg_t *armv7m_reg = reg->arch_info;
- target_t *target = armv7m_reg->target;
- u32 value = buf_get_u32(buf, 0, 32);
-
+ struct arm_reg *armv7m_reg = reg->arch_info;
+ struct target *target = armv7m_reg->target;
+
if (target->state != TARGET_HALTED)
- {
return ERROR_TARGET_NOT_HALTED;
- }
-
- buf_set_u32(reg->value, 0, 32, value);
- reg->dirty = 1;
- reg->valid = 1;
+
+ buf_cpy(buf, reg->value, reg->size);
+ reg->dirty = true;
+ reg->valid = true;
return ERROR_OK;
}
-int armv7m_read_core_reg(struct target_s *target, int num)
+static int armv7m_read_core_reg(struct target *target, struct reg *r,
+ int num, enum arm_mode mode)
{
- u32 reg_value;
+ uint32_t reg_value;
int retval;
- armv7m_core_reg_t * armv7m_core_reg;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
- if ((num < 0) || (num >= ARMV7NUMCOREREGS))
- return ERROR_INVALID_ARGUMENTS;
-
- armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
- retval = armv7m->load_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, ®_value);
- buf_set_u32(armv7m->core_cache->reg_list[num].value, 0, 32, reg_value);
- armv7m->core_cache->reg_list[num].valid = 1;
- armv7m->core_cache->reg_list[num].dirty = 0;
-
- return ERROR_OK;
+ struct arm_reg *armv7m_core_reg;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+
+ assert(num < (int)armv7m->arm.core_cache->num_regs);
+
+ armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
+
+ if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
+ /* map D0..D15 to S0..S31 */
+ size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
+ retval = armv7m->load_core_reg_u32(target, regidx, ®_value);
+ if (retval != ERROR_OK)
+ return retval;
+ buf_set_u32(armv7m->arm.core_cache->reg_list[num].value,
+ 0, 32, reg_value);
+ retval = armv7m->load_core_reg_u32(target, regidx + 1, ®_value);
+ if (retval != ERROR_OK)
+ return retval;
+ buf_set_u32(armv7m->arm.core_cache->reg_list[num].value + 4,
+ 0, 32, reg_value);
+ } else {
+ retval = armv7m->load_core_reg_u32(target,
+ armv7m_core_reg->num, ®_value);
+ if (retval != ERROR_OK)
+ return retval;
+ buf_set_u32(armv7m->arm.core_cache->reg_list[num].value, 0, 32, reg_value);
+ }
+
+ armv7m->arm.core_cache->reg_list[num].valid = true;
+ armv7m->arm.core_cache->reg_list[num].dirty = false;
+
+ return retval;
}
-int armv7m_write_core_reg(struct target_s *target, int num)
+static int armv7m_write_core_reg(struct target *target, struct reg *r,
+ int num, enum arm_mode mode, uint8_t *value)
{
int retval;
- u32 reg_value;
- armv7m_core_reg_t *armv7m_core_reg;
-
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
- if ((num < 0) || (num >= ARMV7NUMCOREREGS))
- return ERROR_INVALID_ARGUMENTS;
-
- reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32);
- armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info;
- retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
- if (retval != ERROR_OK)
- {
- ERROR("JTAG failure");
- armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
- return ERROR_JTAG_DEVICE_ERROR;
+ struct arm_reg *armv7m_core_reg;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+
+ assert(num < (int)armv7m->arm.core_cache->num_regs);
+
+ armv7m_core_reg = armv7m->arm.core_cache->reg_list[num].arch_info;
+
+ if ((armv7m_core_reg->num >= ARMV7M_D0) && (armv7m_core_reg->num <= ARMV7M_D15)) {
+ /* map D0..D15 to S0..S31 */
+ size_t regidx = ARMV7M_S0 + 2 * (armv7m_core_reg->num - ARMV7M_D0);
+
+ uint32_t t = buf_get_u32(value, 0, 32);
+ retval = armv7m->store_core_reg_u32(target, regidx, t);
+ if (retval != ERROR_OK)
+ goto out_error;
+
+ t = buf_get_u32(value + 4, 0, 32);
+ retval = armv7m->store_core_reg_u32(target, regidx + 1, t);
+ if (retval != ERROR_OK)
+ goto out_error;
+ } else {
+ uint32_t t = buf_get_u32(value, 0, 32);
+
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, t);
+ retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->num, t);
+ if (retval != ERROR_OK)
+ goto out_error;
}
- DEBUG("write core reg %i value 0x%x", num , reg_value);
- armv7m->core_cache->reg_list[num].valid = 1;
- armv7m->core_cache->reg_list[num].dirty = 0;
-
+
+ armv7m->arm.core_cache->reg_list[num].valid = true;
+ armv7m->arm.core_cache->reg_list[num].dirty = false;
+
return ERROR_OK;
+
+out_error:
+ LOG_ERROR("Error setting register");
+ armv7m->arm.core_cache->reg_list[num].dirty = armv7m->arm.core_cache->reg_list[num].valid;
+ return ERROR_JTAG_DEVICE_ERROR;
}
-int armv7m_invalidate_core_regs(target_t *target)
+/**
+ * Returns generic ARM userspace registers to GDB.
+ */
+int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
+ int *reg_list_size, enum target_register_class reg_class)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
int i;
-
- for (i = 0; i < armv7m->core_cache->num_regs; i++)
- {
- armv7m->core_cache->reg_list[i].valid = 0;
- armv7m->core_cache->reg_list[i].dirty = 0;
- }
-
+
+ if (reg_class == REG_CLASS_ALL)
+ *reg_list_size = armv7m->arm.core_cache->num_regs;
+ else
+ *reg_list_size = ARMV7M_NUM_CORE_REGS;
+
+ *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+ if (*reg_list == NULL)
+ return ERROR_FAIL;
+
+ for (i = 0; i < *reg_list_size; i++)
+ (*reg_list)[i] = &armv7m->arm.core_cache->reg_list[i];
+
return ERROR_OK;
}
-int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
+/** Runs a Thumb algorithm in the target. */
+int armv7m_run_algorithm(struct target *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ target_addr_t entry_point, target_addr_t exit_point,
+ int timeout_ms, void *arch_info)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
- int i;
-
- if (target->state != TARGET_HALTED)
- {
- return ERROR_TARGET_NOT_HALTED;
- }
-
- *reg_list_size = 26;
- *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
-
- /* TODOLATER correct list of registers, names ? */
- for (i = 0; i < *reg_list_size; i++)
- {
- if (i < ARMV7NUMCOREREGS)
- (*reg_list)[i] = &armv7m->process_context->reg_list[i];
- //(*reg_list)[i] = &armv7m->core_cache->reg_list[i];
- else
- (*reg_list)[i] = &armv7m_gdb_dummy_fp_reg;
- }
- /* ARMV7M is always in thumb mode, try to make GDB understand this if it does not support this arch */
- armv7m->process_context->reg_list[15].value[0] |= 1;
- (*reg_list)[25] = &armv7m->process_context->reg_list[ARMV7M_xPSR];
- return ERROR_OK;
+ int retval;
+
+ retval = armv7m_start_algorithm(target,
+ num_mem_params, mem_params,
+ num_reg_params, reg_params,
+ entry_point, exit_point,
+ arch_info);
+
+ if (retval == ERROR_OK)
+ retval = armv7m_wait_algorithm(target,
+ num_mem_params, mem_params,
+ num_reg_params, reg_params,
+ exit_point, timeout_ms,
+ arch_info);
+
+ return retval;
}
-int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
+/** Starts a Thumb algorithm in the target. */
+int armv7m_start_algorithm(struct target *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ target_addr_t entry_point, target_addr_t exit_point,
+ void *arch_info)
{
- // get pointers to arch-specific information
- armv7m_common_t *armv7m = target->arch_info;
- armv7m_algorithm_t *armv7m_algorithm_info = arch_info;
- enum armv7m_state core_state = armv7m->core_state;
- enum armv7m_mode core_mode = armv7m->core_mode;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
+ enum arm_mode core_mode = armv7m->arm.core_mode;
int retval = ERROR_OK;
- u32 pc;
- int exit_breakpoint_size = 0;
- int i;
-
- armv7m->core_state = core_state;
- armv7m->core_mode = core_mode;
- if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
- {
- ERROR("current target isn't an ARMV7M target");
+ /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
+ * at the exit point */
+
+ if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
+ LOG_ERROR("current target isn't an ARMV7M target");
return ERROR_TARGET_INVALID;
}
-
- if (target->state != TARGET_HALTED)
- {
- WARNING("target not halted");
+
+ if (target->state != TARGET_HALTED) {
+ LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
-
- /* refresh core register cache */
- /* Not needed if core register cache is always consistent with target process state */
- armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
-
- for (i = 0; i < num_mem_params; i++)
- {
- target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+
+ /* refresh core register cache
+ * Not needed if core register cache is always consistent with target process state */
+ for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
+
+ armv7m_algorithm_info->context[i] = buf_get_u32(
+ armv7m->arm.core_cache->reg_list[i].value,
+ 0,
+ 32);
}
-
- for (i = 0; i < num_reg_params; i++)
- {
- reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
- u32 regvalue;
-
- if (!reg)
- {
- ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
+
+ for (int i = 0; i < num_mem_params; i++) {
+ if (mem_params[i].direction == PARAM_IN)
+ continue;
+ retval = target_write_buffer(target, mem_params[i].address,
+ mem_params[i].size,
+ mem_params[i].value);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ for (int i = 0; i < num_reg_params; i++) {
+ if (reg_params[i].direction == PARAM_IN)
+ continue;
+
+ struct reg *reg =
+ register_get_by_name(armv7m->arm.core_cache, reg_params[i].reg_name, 0);
+/* uint32_t regvalue; */
+
+ if (!reg) {
+ LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
-
- if (reg->size != reg_params[i].size)
- {
- ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
+
+ if (reg->size != reg_params[i].size) {
+ LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
+ reg_params[i].reg_name);
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
-
- regvalue = buf_get_u32(reg_params[i].value, 0, 32);
+
+/* regvalue = buf_get_u32(reg_params[i].value, 0, 32); */
armv7m_set_core_reg(reg, reg_params[i].value);
}
-
- /* ARMV7M always runs in Thumb state */
- exit_breakpoint_size = 2;
- if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_SOFT)) != ERROR_OK)
+
{
- ERROR("can't add breakpoint to finish algorithm execution");
- return ERROR_TARGET_FAILURE;
+ /*
+ * Ensure xPSR.T is set to avoid trying to run things in arm
+ * (non-thumb) mode, which armv7m does not support.
+ *
+ * We do this by setting the entirety of xPSR, which should
+ * remove all the unknowns about xPSR state.
+ *
+ * Because xPSR.T is populated on reset from the vector table,
+ * it might be 0 if the vector table has "bad" data in it.
+ */
+ struct reg *reg = &armv7m->arm.core_cache->reg_list[ARMV7M_xPSR];
+ buf_set_u32(reg->value, 0, 32, 0x01000000);
+ reg->valid = true;
+ reg->dirty = true;
}
-
- /* This code relies on the target specific resume() and poll()->debug_entry()
- sequence to write register values to the processor and the read them back */
- target->type->resume(target, 0, entry_point, 1, 1);
- target->type->poll(target);
-
- while (target->state != TARGET_HALTED)
- {
- usleep(5000);
- target->type->poll(target);
- if ((timeout_ms -= 5) <= 0)
- {
- ERROR("timeout waiting for algorithm to complete, trying to halt target");
- target->type->halt(target);
- timeout_ms = 1000;
- while (target->state != TARGET_HALTED)
- {
- usleep(10000);
- target->type->poll(target);
- if ((timeout_ms -= 10) <= 0)
- {
- ERROR("target didn't reenter debug state, exiting");
- exit(-1);
- }
- }
- armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
- DEBUG("failed algoritm halted at 0x%x ", pc);
- retval = ERROR_TARGET_TIMEOUT;
+
+ if (armv7m_algorithm_info->core_mode != ARM_MODE_ANY &&
+ armv7m_algorithm_info->core_mode != core_mode) {
+
+ /* we cannot set ARM_MODE_HANDLER, so use ARM_MODE_THREAD instead */
+ if (armv7m_algorithm_info->core_mode == ARM_MODE_HANDLER) {
+ armv7m_algorithm_info->core_mode = ARM_MODE_THREAD;
+ LOG_INFO("ARM_MODE_HANDLER not currently supported, using ARM_MODE_THREAD instead");
}
+
+ LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
+ buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
+ 0, 1, armv7m_algorithm_info->core_mode);
+ armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
+ armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
+ }
+
+ /* save previous core mode */
+ armv7m_algorithm_info->core_mode = core_mode;
+
+ retval = target_resume(target, 0, entry_point, 1, 1);
+
+ return retval;
+}
+
+/** Waits for an algorithm in the target. */
+int armv7m_wait_algorithm(struct target *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ target_addr_t exit_point, int timeout_ms,
+ void *arch_info)
+{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
+ int retval = ERROR_OK;
+ uint32_t pc;
+
+ /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
+ * at the exit point */
+
+ if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) {
+ LOG_ERROR("current target isn't an ARMV7M target");
+ return ERROR_TARGET_INVALID;
}
-
- breakpoint_remove(target, exit_point);
-
+
+ retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
+ /* If the target fails to halt due to the breakpoint, force a halt */
+ if (retval != ERROR_OK || target->state != TARGET_HALTED) {
+ retval = target_halt(target);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_wait_state(target, TARGET_HALTED, 500);
+ if (retval != ERROR_OK)
+ return retval;
+ return ERROR_TARGET_TIMEOUT;
+ }
+
+ armv7m->load_core_reg_u32(target, 15, &pc);
+ if (exit_point && (pc != exit_point)) {
+ LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
+ pc,
+ exit_point);
+ return ERROR_TARGET_TIMEOUT;
+ }
+
/* Read memory values to mem_params[] */
- for (i = 0; i < num_mem_params; i++)
- {
- if (mem_params[i].direction != PARAM_OUT)
- target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
+ for (int i = 0; i < num_mem_params; i++) {
+ if (mem_params[i].direction != PARAM_OUT) {
+ retval = target_read_buffer(target, mem_params[i].address,
+ mem_params[i].size,
+ mem_params[i].value);
+ if (retval != ERROR_OK)
+ return retval;
+ }
}
-
+
/* Copy core register values to reg_params[] */
- for (i = 0; i < num_reg_params; i++)
- {
- if (reg_params[i].direction != PARAM_OUT)
- {
- reg_t *reg = register_get_by_name(armv7m->debug_context, reg_params[i].reg_name, 0);
-
- if (!reg)
- {
- ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
- exit(-1);
+ for (int i = 0; i < num_reg_params; i++) {
+ if (reg_params[i].direction != PARAM_OUT) {
+ struct reg *reg = register_get_by_name(armv7m->arm.core_cache,
+ reg_params[i].reg_name,
+ 0);
+
+ if (!reg) {
+ LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
-
- if (reg->size != reg_params[i].size)
- {
- ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
- exit(-1);
+
+ if (reg->size != reg_params[i].size) {
+ LOG_ERROR(
+ "BUG: register '%s' size doesn't match reg_params[i].size",
+ reg_params[i].reg_name);
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
}
}
-
+
+ for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
+ uint32_t regvalue;
+ regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
+ if (regvalue != armv7m_algorithm_info->context[i]) {
+ LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
+ armv7m->arm.core_cache->reg_list[i].name,
+ armv7m_algorithm_info->context[i]);
+ buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
+ 0, 32, armv7m_algorithm_info->context[i]);
+ armv7m->arm.core_cache->reg_list[i].valid = true;
+ armv7m->arm.core_cache->reg_list[i].dirty = true;
+ }
+ }
+
+ /* restore previous core mode */
+ if (armv7m_algorithm_info->core_mode != armv7m->arm.core_mode) {
+ LOG_DEBUG("restoring core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
+ buf_set_u32(armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].value,
+ 0, 1, armv7m_algorithm_info->core_mode);
+ armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].dirty = true;
+ armv7m->arm.core_cache->reg_list[ARMV7M_CONTROL].valid = true;
+ }
+
+ armv7m->arm.core_mode = armv7m_algorithm_info->core_mode;
+
return retval;
}
-int armv7m_arch_state(struct target_s *target)
+/** Logs summary of ARMv7-M state for a halted target. */
+int armv7m_arch_state(struct target *target)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
- USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
- armv7m_state_strings[armv7m->core_state],
- target_debug_reason_strings[target->debug_reason],
- armv7m_mode_strings[armv7m->core_mode],
- armv7m_exception_string(armv7m->exception_number),
- buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
- buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32));
-
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct arm *arm = &armv7m->arm;
+ uint32_t ctrl, sp;
+
+ /* avoid filling log waiting for fileio reply */
+ if (target->semihosting && target->semihosting->hit_fileio)
+ return ERROR_OK;
+
+ ctrl = buf_get_u32(arm->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32);
+ sp = buf_get_u32(arm->core_cache->reg_list[ARMV7M_R13].value, 0, 32);
+
+ LOG_USER("target halted due to %s, current mode: %s %s\n"
+ "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32 "%s%s",
+ debug_reason_name(target),
+ arm_mode_name(arm->core_mode),
+ armv7m_exception_string(armv7m->exception_number),
+ buf_get_u32(arm->cpsr->value, 0, 32),
+ buf_get_u32(arm->pc->value, 0, 32),
+ (ctrl & 0x02) ? 'p' : 'm',
+ sp,
+ (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
+ (target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
+
return ERROR_OK;
}
-reg_cache_t *armv7m_build_reg_cache(target_t *target)
+static const struct reg_arch_type armv7m_reg_type = {
+ .get = armv7m_get_core_reg,
+ .set = armv7m_set_core_reg,
+};
+
+/** Builds cache of architecturally defined registers. */
+struct reg_cache *armv7m_build_reg_cache(struct target *target)
{
- /* get pointers to arch-specific information */
- armv7m_common_t *armv7m = target->arch_info;
-
- int num_regs = ARMV7NUMCOREREGS;
- reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
- reg_cache_t *cache = malloc(sizeof(reg_cache_t));
- reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
- armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct arm *arm = &armv7m->arm;
+ int num_regs = ARMV7M_NUM_REGS;
+ struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
+ struct reg_cache *cache = malloc(sizeof(struct reg_cache));
+ struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
+ struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg));
+ struct reg_feature *feature;
int i;
-
- if (armv7m_core_reg_arch_type == -1)
- armv7m_core_reg_arch_type = register_reg_arch_type(armv7m_get_core_reg, armv7m_set_core_reg);
-
- /* Build the process context cache */
+
+ /* Build the process context cache */
cache->name = "arm v7m registers";
cache->next = NULL;
cache->reg_list = reg_list;
cache->num_regs = num_regs;
(*cache_p) = cache;
- armv7m->core_cache = cache;
- armv7m->process_context = cache;
-
- for (i = 0; i < num_regs; i++)
- {
- arch_info[i] = armv7m_core_reg_list_arch_info[i];
+
+ for (i = 0; i < num_regs; i++) {
+ arch_info[i].num = armv7m_regs[i].id;
arch_info[i].target = target;
- arch_info[i].armv7m_common = armv7m;
- reg_list[i].name = armv7m_core_reg_list[i];
- reg_list[i].size = 32;
- reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
- reg_list[i].bitfield_desc = NULL;
- reg_list[i].num_bitfields = 0;
- reg_list[i].arch_type = armv7m_core_reg_arch_type;
+ arch_info[i].arm = arm;
+
+ reg_list[i].name = armv7m_regs[i].name;
+ reg_list[i].size = armv7m_regs[i].bits;
+ size_t storage_size = DIV_ROUND_UP(armv7m_regs[i].bits, 8);
+ if (storage_size < 4)
+ storage_size = 4;
+ reg_list[i].value = calloc(1, storage_size);
+ reg_list[i].dirty = false;
+ reg_list[i].valid = false;
+ reg_list[i].type = &armv7m_reg_type;
reg_list[i].arch_info = &arch_info[i];
+
+ reg_list[i].group = armv7m_regs[i].group;
+ reg_list[i].number = i;
+ reg_list[i].exist = true;
+ reg_list[i].caller_save = true; /* gdb defaults to true */
+
+ feature = calloc(1, sizeof(struct reg_feature));
+ if (feature) {
+ feature->name = armv7m_regs[i].feature;
+ reg_list[i].feature = feature;
+ } else
+ LOG_ERROR("unable to allocate feature list");
+
+ reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
+ if (reg_list[i].reg_data_type)
+ reg_list[i].reg_data_type->type = armv7m_regs[i].type;
+ else
+ LOG_ERROR("unable to allocate reg type list");
}
- /* Build the debug context cache*/
- cache = malloc(sizeof(reg_cache_t));
- reg_list = malloc(sizeof(reg_t) * num_regs);
+ arm->cpsr = reg_list + ARMV7M_xPSR;
+ arm->pc = reg_list + ARMV7M_PC;
+ arm->core_cache = cache;
- cache->name = "arm v7m debug registers";
- cache->next = NULL;
- cache->reg_list = reg_list;
- cache->num_regs = num_regs;
- armv7m->debug_context = cache;
- armv7m->process_context->next = cache;
-
- for (i = 0; i < num_regs; i++)
- {
- reg_list[i].name = armv7m_core_dbgreg_list[i];
- reg_list[i].size = 32;
- reg_list[i].value = calloc(1, 4);
- reg_list[i].dirty = 0;
- reg_list[i].valid = 0;
- reg_list[i].bitfield_desc = NULL;
- reg_list[i].num_bitfields = 0;
- reg_list[i].arch_type = armv7m_core_reg_arch_type;
- reg_list[i].arch_info = &arch_info[i];
- }
-
return cache;
}
-int armv7m_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+void armv7m_free_reg_cache(struct target *target)
{
- armv7m_build_reg_cache(target);
-
- return ERROR_OK;
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct arm *arm = &armv7m->arm;
+ struct reg_cache *cache;
+ struct reg *reg;
+ unsigned int i;
+
+ cache = arm->core_cache;
+
+ if (!cache)
+ return;
+
+ for (i = 0; i < cache->num_regs; i++) {
+ reg = &cache->reg_list[i];
+
+ free(reg->feature);
+ free(reg->reg_data_type);
+ free(reg->value);
+ }
+
+ free(cache->reg_list[0].arch_info);
+ free(cache->reg_list);
+ free(cache);
+
+ arm->core_cache = NULL;
}
-int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m)
+static int armv7m_setup_semihosting(struct target *target, int enable)
{
- /* register arch-specific functions */
-
- target->arch_info = armv7m;
- armv7m->core_state = ARMV7M_STATE_THUMB;
- armv7m->read_core_reg = armv7m_read_core_reg;
- armv7m->write_core_reg = armv7m_write_core_reg;
-
+ /* nothing todo for armv7m */
return ERROR_OK;
}
-int armv7m_register_commands(struct command_context_s *cmd_ctx)
+/** Sets up target as a generic ARMv7-M core */
+int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
{
- return ERROR_OK;
+ struct arm *arm = &armv7m->arm;
+
+ armv7m->common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m->fp_feature = FP_NONE;
+ armv7m->trace_config.trace_bus_id = 1;
+ /* Enable stimulus port #0 by default */
+ armv7m->trace_config.itm_ter[0] = 1;
+
+ arm->core_type = ARM_MODE_THREAD;
+ arm->arch_info = armv7m;
+ arm->setup_semihosting = armv7m_setup_semihosting;
+
+ arm->read_core_reg = armv7m_read_core_reg;
+ arm->write_core_reg = armv7m_write_core_reg;
+
+ return arm_init_arch_info(target, arm);
}
-int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
+/** Generates a CRC32 checksum of a memory region. */
+int armv7m_checksum_memory(struct target *target,
+ target_addr_t address, uint32_t count, uint32_t *checksum)
{
- working_area_t *crc_algorithm;
- armv7m_algorithm_t armv7m_info;
- reg_param_t reg_params[2];
+ struct working_area *crc_algorithm;
+ struct armv7m_algorithm armv7m_info;
+ struct reg_param reg_params[2];
int retval;
-
- u16 cortex_m3_crc_code[] = {
- 0x4602, /* mov r2, r0 */
- 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
- 0x460B, /* mov r3, r1 */
- 0xF04F, 0x0400, /* mov r4, #0 */
- 0xE013, /* b ncomp */
- /* nbyte: */
- 0x5D11, /* ldrb r1, [r2, r4] */
- 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
- 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
-
- 0xF04F, 0x0500, /* mov r5, #0 */
- /* loop: */
- 0x2800, /* cmp r0, #0 */
- 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
- 0xF105, 0x0501, /* add r5, r5, #1 */
- 0x4630, /* mov r0, r6 */
- 0xBFB8, /* it lt */
- 0xEA86, 0x0007, /* eor r0, r6, r7 */
- 0x2D08, /* cmp r5, #8 */
- 0xD1F4, /* bne loop */
-
- 0xF104, 0x0401, /* add r4, r4, #1 */
- /* ncomp: */
- 0x429C, /* cmp r4, r3 */
- 0xD1E9, /* bne nbyte */
- /* end: */
- 0xE7FE, /* b end */
- 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
+
+ static const uint8_t cortex_m_crc_code[] = {
+#include "../../contrib/loaders/checksum/armv7m_crc.inc"
};
- int i;
-
- if (target_alloc_working_area(target, sizeof(cortex_m3_crc_code), &crc_algorithm) != ERROR_OK)
- {
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
-
- /* convert flash writing code into a buffer in target endianness */
- for (i = 0; i < (sizeof(cortex_m3_crc_code)/sizeof(u16)); i++)
- target_write_u16(target, crc_algorithm->address + i*sizeof(u16), cortex_m3_crc_code[i]);
-
+ retval = target_alloc_working_area(target, sizeof(cortex_m_crc_code), &crc_algorithm);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_buffer(target, crc_algorithm->address,
+ sizeof(cortex_m_crc_code), (uint8_t *)cortex_m_crc_code);
+ if (retval != ERROR_OK)
+ goto cleanup;
+
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
- armv7m_info.core_mode = ARMV7M_MODE_ANY;
- armv7m_info.core_state = ARMV7M_STATE_THUMB;
-
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
-
+
buf_set_u32(reg_params[0].value, 0, 32, address);
buf_set_u32(reg_params[1].value, 0, 32, count);
-
- if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
- crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
- {
- ERROR("error executing cortex_m3 crc algorithm");
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- target_free_working_area(target, crc_algorithm);
- return retval;
- }
-
- *checksum = buf_get_u32(reg_params[0].value, 0, 32);
-
+
+ int timeout = 20000 * (1 + (count / (1024 * 1024)));
+
+ retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address,
+ crc_algorithm->address + (sizeof(cortex_m_crc_code) - 6),
+ timeout, &armv7m_info);
+
+ if (retval == ERROR_OK)
+ *checksum = buf_get_u32(reg_params[0].value, 0, 32);
+ else
+ LOG_ERROR("error executing cortex_m crc algorithm");
+
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
-
+
+cleanup:
target_free_working_area(target, crc_algorithm);
-
+
+ return retval;
+}
+
+/** Checks an array of memory regions whether they are erased. */
+int armv7m_blank_check_memory(struct target *target,
+ struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
+{
+ struct working_area *erase_check_algorithm;
+ struct working_area *erase_check_params;
+ struct reg_param reg_params[2];
+ struct armv7m_algorithm armv7m_info;
+ int retval;
+
+ static bool timed_out;
+
+ static const uint8_t erase_check_code[] = {
+#include "../../contrib/loaders/erase_check/armv7m_erase_check.inc"
+ };
+
+ const uint32_t code_size = sizeof(erase_check_code);
+
+ /* make sure we have a working area */
+ if (target_alloc_working_area(target, code_size,
+ &erase_check_algorithm) != ERROR_OK)
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+
+ retval = target_write_buffer(target, erase_check_algorithm->address,
+ code_size, erase_check_code);
+ if (retval != ERROR_OK)
+ goto cleanup1;
+
+ /* prepare blocks array for algo */
+ struct algo_block {
+ union {
+ uint32_t size;
+ uint32_t result;
+ };
+ uint32_t address;
+ };
+
+ uint32_t avail = target_get_working_area_avail(target);
+ int blocks_to_check = avail / sizeof(struct algo_block) - 1;
+ if (num_blocks < blocks_to_check)
+ blocks_to_check = num_blocks;
+
+ struct algo_block *params = malloc((blocks_to_check+1)*sizeof(struct algo_block));
+ if (params == NULL) {
+ retval = ERROR_FAIL;
+ goto cleanup1;
+ }
+
+ int i;
+ uint32_t total_size = 0;
+ for (i = 0; i < blocks_to_check; i++) {
+ total_size += blocks[i].size;
+ target_buffer_set_u32(target, (uint8_t *)&(params[i].size),
+ blocks[i].size / sizeof(uint32_t));
+ target_buffer_set_u32(target, (uint8_t *)&(params[i].address),
+ blocks[i].address);
+ }
+ target_buffer_set_u32(target, (uint8_t *)&(params[blocks_to_check].size), 0);
+
+ uint32_t param_size = (blocks_to_check + 1) * sizeof(struct algo_block);
+ if (target_alloc_working_area(target, param_size,
+ &erase_check_params) != ERROR_OK) {
+ retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ goto cleanup2;
+ }
+
+ retval = target_write_buffer(target, erase_check_params->address,
+ param_size, (uint8_t *)params);
+ if (retval != ERROR_OK)
+ goto cleanup3;
+
+ uint32_t erased_word = erased_value | (erased_value << 8)
+ | (erased_value << 16) | (erased_value << 24);
+
+ LOG_DEBUG("Starting erase check of %d blocks, parameters@"
+ TARGET_ADDR_FMT, blocks_to_check, erase_check_params->address);
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
+ buf_set_u32(reg_params[0].value, 0, 32, erase_check_params->address);
+
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
+ buf_set_u32(reg_params[1].value, 0, 32, erased_word);
+
+ /* assume CPU clk at least 1 MHz */
+ int timeout = (timed_out ? 30000 : 2000) + total_size * 3 / 1000;
+
+ retval = target_run_algorithm(target,
+ 0, NULL,
+ ARRAY_SIZE(reg_params), reg_params,
+ erase_check_algorithm->address,
+ erase_check_algorithm->address + (code_size - 2),
+ timeout,
+ &armv7m_info);
+
+ timed_out = retval == ERROR_TARGET_TIMEOUT;
+ if (retval != ERROR_OK && !timed_out)
+ goto cleanup4;
+
+ retval = target_read_buffer(target, erase_check_params->address,
+ param_size, (uint8_t *)params);
+ if (retval != ERROR_OK)
+ goto cleanup4;
+
+ for (i = 0; i < blocks_to_check; i++) {
+ uint32_t result = target_buffer_get_u32(target,
+ (uint8_t *)&(params[i].result));
+ if (result != 0 && result != 1)
+ break;
+
+ blocks[i].result = result;
+ }
+ if (i && timed_out)
+ LOG_INFO("Slow CPU clock: %d blocks checked, %d remain. Continuing...", i, num_blocks-i);
+
+ retval = i; /* return number of blocks really checked */
+
+cleanup4:
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+
+cleanup3:
+ target_free_working_area(target, erase_check_params);
+cleanup2:
+ free(params);
+cleanup1:
+ target_free_working_area(target, erase_check_algorithm);
+
+ return retval;
+}
+
+int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
+{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct reg *r = armv7m->arm.pc;
+ bool result = false;
+
+
+ /* if we halted last time due to a bkpt instruction
+ * then we have to manually step over it, otherwise
+ * the core will break again */
+
+ if (target->debug_reason == DBG_REASON_BREAKPOINT) {
+ uint16_t op;
+ uint32_t pc = buf_get_u32(r->value, 0, 32);
+
+ pc &= ~1;
+ if (target_read_u16(target, pc, &op) == ERROR_OK) {
+ if ((op & 0xFF00) == 0xBE00) {
+ pc = buf_get_u32(r->value, 0, 32) + 2;
+ buf_set_u32(r->value, 0, 32, pc);
+ r->dirty = true;
+ r->valid = true;
+ result = true;
+ LOG_DEBUG("Skipping over BKPT instruction");
+ }
+ }
+ }
+
+ if (inst_found)
+ *inst_found = result;
+
return ERROR_OK;
}
+const struct command_registration armv7m_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
projects / fw / openocd / blobdiff