* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
LOG_DEBUG("cl %" PRId32, cl);
do {
+ keep_alive();
c_way = size->way;
do {
uint32_t value = (c_index << size->index_shift)
} while (c_index >= 0);
done:
+ keep_alive();
return retval;
}
} else
retval = armv7a_l1_d_cache_clean_inval_all(target);
- /* do outer cache flushing after inner caches have been flushed */
- retval = arm7a_l2x_flush_all_data(target);
+ if (retval != ERROR_OK)
+ return retval;
- return retval;
+ /* do outer cache flushing after inner caches have been flushed */
+ return arm7a_l2x_flush_all_data(target);
}
struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
uint32_t linelen = armv7a_cache->dminline;
uint32_t va_line, va_end;
- int retval;
+ int retval, i = 0;
retval = armv7a_l1_d_cache_sanity_check(target);
if (retval != ERROR_OK)
}
while (va_line < va_end) {
+ if ((i++ & 0x3f) == 0)
+ keep_alive();
/* DCIMVAC - Invalidate data cache line by VA to PoC. */
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(15, 0, 0, 7, 6, 1), va_line);
va_line += linelen;
}
+ keep_alive();
dpm->finish(dpm);
return retval;
done:
LOG_ERROR("d-cache invalidate failed");
+ keep_alive();
dpm->finish(dpm);
return retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm_dpm *dpm = armv7a->arm.dpm;
struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
- uint32_t i, linelen = armv7a_cache->dminline;
- int retval;
+ uint32_t linelen = armv7a_cache->dminline;
+ uint32_t va_line, va_end;
+ int retval, i = 0;
retval = armv7a_l1_d_cache_sanity_check(target);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
goto done;
- for (i = 0; i < size; i += linelen) {
- uint32_t offs = virt + i;
+ va_line = virt & (-linelen);
+ va_end = virt + size;
+ while (va_line < va_end) {
+ if ((i++ & 0x3f) == 0)
+ keep_alive();
/* DCCMVAC - Data Cache Clean by MVA to PoC */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 10, 1), offs);
+ ARMV4_5_MCR(15, 0, 0, 7, 10, 1), va_line);
if (retval != ERROR_OK)
goto done;
+ va_line += linelen;
}
+
+ keep_alive();
+ dpm->finish(dpm);
return retval;
done:
LOG_ERROR("d-cache invalidate failed");
+ keep_alive();
dpm->finish(dpm);
return retval;
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm_dpm *dpm = armv7a->arm.dpm;
struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
- uint32_t i, linelen = armv7a_cache->dminline;
- int retval;
+ uint32_t linelen = armv7a_cache->dminline;
+ uint32_t va_line, va_end;
+ int retval, i = 0;
retval = armv7a_l1_d_cache_sanity_check(target);
if (retval != ERROR_OK)
if (retval != ERROR_OK)
goto done;
- for (i = 0; i < size; i += linelen) {
- uint32_t offs = virt + i;
+ va_line = virt & (-linelen);
+ va_end = virt + size;
+ while (va_line < va_end) {
+ if ((i++ & 0x3f) == 0)
+ keep_alive();
/* DCCIMVAC */
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 14, 1), offs);
+ ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
if (retval != ERROR_OK)
goto done;
+ va_line += linelen;
}
+
+ keep_alive();
+ dpm->finish(dpm);
return retval;
done:
LOG_ERROR("d-cache invalidate failed");
+ keep_alive();
dpm->finish(dpm);
return retval;
&armv7a->armv7a_mmu.armv7a_cache;
uint32_t linelen = armv7a_cache->iminline;
uint32_t va_line, va_end;
- int retval;
+ int retval, i = 0;
retval = armv7a_l1_i_cache_sanity_check(target);
if (retval != ERROR_OK)
va_end = virt + size;
while (va_line < va_end) {
+ if ((i++ & 0x3f) == 0)
+ keep_alive();
/* ICIMVAU - Invalidate instruction cache by VA to PoU. */
retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MCR(15, 0, 0, 7, 5, 1), va_line);
goto done;
va_line += linelen;
}
+ keep_alive();
+ dpm->finish(dpm);
return retval;
done:
LOG_ERROR("i-cache invalidate failed");
+ keep_alive();
dpm->finish(dpm);
return retval;
* We assume that target core was chosen correctly. It means if same data
* was handled by two cores, other core will loose the changes. Since it
* is impossible to know (FIXME) which core has correct data, keep in mind
- * that some kind of data lost or korruption is possible.
+ * that some kind of data lost or corruption is possible.
* Possible scenario:
* - core1 loaded and changed data on 0x12345678
* - we halted target and modified same data on core0
struct target *target = get_current_target(CMD_CTX);
struct armv7a_common *armv7a = target_to_armv7a(target);
- return armv7a_handle_cache_info_command(CMD_CTX,
+ return armv7a_handle_cache_info_command(CMD,
&armv7a->armv7a_mmu.armv7a_cache);
}
struct armv7a_common *armv7a = target_to_armv7a(target);
if (CMD_ARGC == 0) {
- command_print(CMD_CTX, "auto cache is %s",
+ command_print(CMD, "auto cache is %s",
armv7a->armv7a_mmu.armv7a_cache.auto_cache_enabled ? "enabled" : "disabled");
return ERROR_OK;
}
COMMAND_REGISTRATION_DONE
};
-const struct command_registration arm7a_l1_di_cache_group_handlers[] = {
+static const struct command_registration arm7a_l1_di_cache_group_handlers[] = {
{
.name = "info",
.handler = arm7a_l1_cache_info_cmd,
.mode = COMMAND_ANY,
- .help = "print cache realted information",
+ .help = "print cache related information",
.usage = "",
},
{
COMMAND_REGISTRATION_DONE
};
-const struct command_registration arm7a_cache_group_handlers[] = {
+static const struct command_registration arm7a_cache_group_handlers[] = {
{
.name = "auto",
.handler = arm7a_cache_disable_auto_cmd,
projects / fw / openocd / blobdiff